M1AFS250-FGG256I Actel Corporation, M1AFS250-FGG256I Datasheet - Page 178

• Manufacturer Part Number: M1AFS250-FGG256I
• Description: Actel Fusion Family Of Mixed Signal Fpgas
• Manufacturer: Actel Corporation

Device Architecture
Figure 2-113 • Timing Model
2- 16 2
M-LVDS (Pro IO Banks)
Input LVTTL/LVCMOS
3.3 V (Pro IO banks)
(Pro IO Banks)
LVPECL
BLVDS,
User I/O Characteristics
Timing Model
LVDS,
Operating Conditions: –2 Speed, Commercial Temperature Range (T
Worst-Case VCC = 1.425 V
t
PY
= 0.90 ns
(Non-Registered)
t
PY
t
I/O Module
(Registered)
PY
= 1.22 ns
I/O Module
t
t
ICLKQ
ISUD
= 1.36 ns
= 0.26 ns
= 0.24 ns
D
Q
Register Cell
t
t
CLKQ
SUD
D
= 0.43 ns
Input LVTTL/LVCMOS
3.3 V (Pro IO banks)
= 0.55 ns
Combinational Cell
Q
Combinational Cell
t
PD
t
PD
Combinational Cell
= 0.87 ns
t
PY
= 0.56 ns
t
PD
= 0.90 ns
= 0.47 ns
Combinational Cell
Combinational Cell
Y
Y
R e visio n 1
t
PD
t
PD
Y
= 0.51 ns
= 0.47 ns
Combinational Cell
t
PD
Register Cell
t
t
Y
CLKQ
SUD
(Non-Registered)
Y
D
= 0.49 ns
I/O Module
= 0.43 ns
t
IInput LVTTL/LVCMOS
3.3 V (Pro IO banks)
= 0.55 ns
DP
Q
(Non-Registered)
(Non-Registered)
= 2.74 ns
Y
I/O Module
I/O Module
t
t
DP
DP
t
= 3.30 ns
PY
(Non-Registered)
= 2.39 ns
t
Dp
= 0.90 ns
I/O Module
LVTTL/LVCMOS 3.3 V (Pro I/O banks)
Output drive strength = 12 mA
High slew rate
= 1.60 ns
J
LVTTL/LVCMOS 3.3 V (Pro I/O banks)
Output drive strength = 24 mA
High slew rate
LVCMOS 1.5 V (Pro IO banks)
Output drive strength = 12 mA
High slew
= 70°C),
D
LVPECL (Pro IO banks)
t
t
OCLKQ
OSUD
(Registered)
I/O Module
Q
= 0.31 ns
t
= 0.59 ns
DP
= 1.53 ns
GTL+ 3.3 V