M1AFS250-FGG256I Actel Corporation, M1AFS250-FGG256I Datasheet - Page 123

• Manufacturer Part Number: M1AFS250-FGG256I
• Description: Actel Fusion Family Of Mixed Signal Fpgas
• Manufacturer: Actel Corporation

Actel Fusion Family of Mixed Signal FPGAs
ADC Operation Description
The ADC can be powered down independently of the FPGA core, as an additional control or for power-
saving considerations, via the PWRDWN pin of the Analog Block. The PWRDWN pin controls only the
comparators in the ADC.
Once the ADC has powered up and been released from reset, ADCRESET, the ADC will initiate a
calibration routine designed to provide optimal ADC performance. The Fusion ADC offers a robust
calibration scheme to reduce integrated offset and linearity errors. The offset and linearity errors of the
main capacitor array are compensated for with an 8-bit calibration capacitor array. The offset/linearity
error calibration is carried out in two ways. First, a power-up calibration is carried out when the ADC
comes out of reset. This is initiated by the CALIBRATE output of the Analog Block macro and is a fixed
number of ADC_CLK cycles (3,840 cycles), as shown in
Figure 2-82 on page
2-108. In this mode, the
linearity and offset errors of the capacitors are calibrated.
To further compensate for drift and temperature-dependent effects, every conversion is followed by post-
calibration of either the offset or a bit of the main capacitor array. The post-calibration ensures that, over
time and with temperature, the ADC remains consistent.
After both calibration and the setting of the appropriate configurations, as explained above, the ADC is
ready for operation. Setting the ADCSTART signal high for one clock period will initiate the sample and
conversion of the analog signal on the channel as configured by CHNUMBER[4:0]. The status signals
SAMPLE and BUSY will show when the ADC is sampling and converting
(Figure 2-84 on page
2-109).
Both SAMPLE and BUSY will initially go high. After the ADC has sampled and held the analog signal,
SAMPLE will go low. After the entire operation has completed and the analog signal is converted, BUSY
will go low and DATAVALID will go high. This indicates that the digital result is available on the
RESULT[11:0] pins.
DATAVALID will remain high until a subsequent ADC_START is issued. The DATAVALID goes low on
the rising edge of SYSCLK as shown in
Figure 2-83 on page
2-108. The RESULT signals will be kept
constant until the ADC finishes the subsequent sample. The next sampled RESULT will be available
when DATAVALID goes high again. It is ideal to read the RESULT when DATAVALID is '1'. The
RESULT is latched and remains unchanged until the next DATAVLAID rising edge.
Intra-Conversion
Performing a conversion during power-up, calibration is possible but should be avoided, since the
performance is not guaranteed, as shown in
Table 2-46 on page
2-119. This is described as intra-
conversion.
Figure 2-85 on page 2-109
shows intra-conversion (conversion that starts before a
conversion is finished).
Injected Conversion
A conversion can be interrupted by another conversion. Before the current conversion is finished, a
second conversion can be started by issuing a pulse on signal ADCSTART. When a second conversion
is issued before the current conversion is completed, the current conversion would be dropped and the
ADC would start the second conversion on the rising edge of the SYSCLK. This is known as injected
conversion. Since the ADC is synchronous, the minimum time to issue a second conversion is two clock
cycles of SYSCLK after the previous one.
Figure 2-86 on page 2-110
shows injected conversion
(conversion that starts during the power-up calibration). The total time for calibration still remains 3,840
ADCCLK cycles.
R e v i s i o n 1
2- 107