S9S12P96J0VFTR Freescale Semiconductor, S9S12P96J0VFTR Datasheet - Page 167

• Manufacturer Part Number: S9S12P96J0VFTR
• Description: 16-bit Microcontrollers - MCU 16 BIT 96K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P96J0VFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 16 MHz
• Program Memory Size: 96 KB
• Data Ram Size: 6 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C

6.3.2.7.3
Read: If COMRV[1:0] = 10
Write: If COMRV[1:0] = 10 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the
targeted next state whilst in State3. The matches refer to the match channels of the comparator match
control logic as depicted in
the comparator enable bit in the associated DBGXCTL control register.
The priorities described in
final state has priority followed by the match on the lower channel number (0,1,2).
Freescale Semiconductor
Address: 0x0027
SC[3:0]
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Reset
Field
3–0
W
R
These bits select the targeted next state whilst in State3, based upon the match event.
0
0
7
Debug State Control Register 3 (DBGSCR3)
= Unimplemented or Reserved
Figure 6-11. Debug State Control Register 3 (DBGSCR3)
0
0
6
Table 6-20. State3 — Sequencer Next State Selection
Table 6-36
Figure 6-1
Either Match1 or Match2 to State1....... Match0 to Final State
Either Match1 or Match2 to Final State....... Match0 to State1
Table 6-19. DBGSCR3 Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
Description (Unspecified matches have no effect)
dictate that in the case of simultaneous matches, a match leading to
0
0
5
and described in 6.3.2.8.1. Comparators must be enabled by setting
Match2 to State2........ Match0 to Final State
Match2 to State2........ Match1 to Final State
Match0 to State2....... Match2 to Final State
Match0 to Final State....... Match1 to State1
Match1 to Final State....... Match2 to State1
Match1 to Final State
Match0 to Final State
0
0
4
Match0 to State1
Match1 to State2
Description
Reserved
Reserved
Reserved
Reserved
Reserved
SC3
0
3
SC2
0
2
S12S Debug Module (S12SDBGV2)
SC1
0
1
SC0
0
0
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