S9S12P96J0VFTR Freescale Semiconductor, S9S12P96J0VFTR Datasheet - Page 434

• Manufacturer Part Number: S9S12P96J0VFTR
• Description: 16-bit Microcontrollers - MCU 16 BIT 96K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P96J0VFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 16 MHz
• Program Memory Size: 96 KB
• Data Ram Size: 6 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C

128 KByte Flash Module (S12FTMRC128K1V1)
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV field.
434
FDIVLCK
FDIV[5:0]
FDIVLD
Offset Module Base + 0x0000
Reset
Field
5–0
7
6
W
R
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
Clock Divider Locked
0 FDIV field is open for writing
1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and
Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events
during Flash program and erase algorithms.
BUSCLK frequency. Please refer to
0
7
restore writability to the FDIV field.
The FCLKDIV register must never be written to while a Flash command is
executing (CCIF=0). The FCLKDIV register is writable during the Flash
reset sequence even though CCIF is clear.
= Unimplemented or Reserved
FDIVLCK
0
6
Figure 13-5. Flash Clock Divider Register (FCLKDIV)
Table 13-6. FCLKDIV Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
0
5
Section 13.4.3, “Flash Command Operations,”
CAUTION
Table 13-7
0
4
Description
shows recommended values for FDIV[5:0] based on the
0
3
FDIV[5:0]
0
2
for more information.
Freescale Semiconductor
0
1
0
0