S9S12P96J0VFTR Freescale Semiconductor, S9S12P96J0VFTR Datasheet - Page 213

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S9S12P96J0VFTR

Manufacturer Part Number
S9S12P96J0VFTR
Description
16-bit Microcontrollers - MCU 16 BIT 96K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12P96J0VFTR

Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
16 MHz
Program Memory Size
96 KB
Data Ram Size
6 KB
On-chip Adc
Yes
Operating Supply Voltage
3.15 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
7.3.2.7
This register controls the PLL functionality.
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has
no effect.
Freescale Semiconductor
0x003A
FM1, FM0
Reset
Field
5, 4
W
R
PLL Frequency Modulation Enable Bits — FM1 and FM0 enable frequency modulation on the VCOCLK. This
is to reduce noise emission. The modulation frequency is f
S12CPMU PLL Control Register (CPMUPLL)
0
0
7
Write to this register clears the LOCK and UPOSC status bits.
Care should be taken to ensure that the bus frequency does not exceed the
specified maximum when frequency modulation is enabled.
The frequency modulation (FM1 and FM0) can not be used if the Oscillator
Filter is enabled.
Figure 7-10. S12CPMU PLL Control Register (CPMUPLL)
0
0
6
Table 7-6. CPMUPLL Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
Table 7-7. FM Amplitude selection
FM1
FM1
0
5
0
0
1
1
0
1
0
1
FM0
NOTE
NOTE
NOTE
FM0
0
4
Description
FM Amplitude /
FM off
±1%
±2%
±4%
S12 Clock, Reset and Power Management Unit (S12CPMU)
f
VCO
ref
0
0
3
divided by 16. See
Variation
0
0
2
Table 7-7
0
0
1
for coding.
0
0
0
213

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