LPC1114FHN33/302 NXP Semiconductors, LPC1114FHN33/302 Datasheet - Page 84
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LPC1114FHN33/302
Manufacturer Part Number
LPC1114FHN33/302
Description
ARM Microcontrollers - MCU 32b 32K Flash 42I/O
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1114FN2810212.pdf
(114 pages)
Specifications of LPC1114FHN33/302
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1114
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
32 KB
Data Ram Size
8 KB
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Interface Type
I2C, SPI, SSP, UART
Maximum Operating Temperature
+ 85 C
Number Of Programmable I/os
42
Number Of Timers
4
Program Memory Type
Flash
Factory Pack Quantity
260
Tradename
LPC1100L
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC1114FHN33/302
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Company:
Part Number:
LPC1114FHN33/302:5
Manufacturer:
Intersil
Quantity:
419
Part Number:
LPC1114FHN33/302:5
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
Table 25.
[1]
[2]
[3]
[4]
LPC111X
Product data sheet
Symbol
SPI master (in SPI mode)
T
t
t
t
t
SPI slave (in SPI mode)
T
t
t
t
t
DS
DH
v(Q)
h(Q)
DS
DH
v(Q)
h(Q)
Fig 42. I
cy(clk)
cy(PCLK)
T
main clock frequency f
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
T
T
T
cy(clk)
amb
cy(clk)
amb
SDA
SCL
= 40 C to 85 C.
= 25 C; for normal voltage supply range: V
= (SSPCLKDIV (1 + SCR) CPSDVSR) / f
= 12 T
2
C-bus pins clock timing
Dynamic characteristics of SPI pins in SPI mode
Parameter
clock cycle time
data set-up time
data hold time
data output valid time in SPI mode
data output hold time in SPI mode
PCLK cycle time
data set-up time
data hold time
data output valid time in SPI mode
data output hold time in SPI mode
70 %
30 %
S
10.7 SPI interfaces
t
cy(PCLK)
f
t
f
main
.
70 %
30 %
, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
1 / f
SCL
Conditions
full-duplex mode
when only transmitting
in SPI mode
in SPI mode
in SPI mode
in SPI mode
t
2.4 V V
2.0 V V
1.8 V V
HD;DAT
70 %
30 %
70 %
30 %
All information provided in this document is subject to legal disclaimers.
t
SU;DAT
DD
DD
DD
DD
Rev. 8 — 20 February 2013
3.6 V
< 2.4 V
< 2.0 V
main
= 3.3 V.
. The clock cycle time derived from the SPI bit rate T
70 %
30 %
[1]
[1]
[2]
[2]
[2]
[2]
[2]
[2]
[3][4]
[3][4]
[3][4]
[3][4]
t
LOW
Min
50
40
15
20
24
0
-
0
20
0
3 T
-
-
LPC1110/11/12/13/14/15
cy(PCLK)
t
HIGH
32-bit ARM Cortex-M0 microcontroller
+ 4
70 %
30 %
t
VD;DAT
Typ
-
-
-
-
-
-
-
-
-
-
-
Max
-
-
-
-
10
-
-
-
3 T
2 T
-
cy(PCLK)
cy(PCLK)
cy(clk)
© NXP B.V. 2013. All rights reserved.
is a function of the
+ 11
+ 5
002aaf425
84 of 114
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns