ATAES132-SH-ER Atmel, ATAES132-SH-ER Datasheet - Page 102

• Manufacturer Part Number: ATAES132-SH-ER
• Description: EEPROM AES 32Kbit EE I2C
• Manufacturer: Atmel

Specifications of ATAES132-SH-ER

• Rohs: yes
• Maximum Clock Frequency: 1 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: I2C
• Factory Pack Quantity: 2300

G.3.
G.3.1. Power Up
STATUS Register Behavior in the SPI Interface Mode
The following sections describe the device behavior and expected STATUS register values during commonly performed
operations. See Appendix K for the SPI interface specifications. In SPI Interface mode, there are two ways to read the
STATUS register:
When the ATAES132 is busy or unable to respond for any reason, the WIP status bit is 1b......
The ATAES132 will .......... during power up to indicate that it is not ready to accept a command from the host. When the
power up process is complete (after time t
6 and 7 (see Section L.2.1): the active state, the standby state, or the sleep state.
Upon completion of power up, the command memory buffer is empty, the response memory buffer are all 0xFF's, and the
ChipState = 0xFFFF. The default EEPROM address is set to 0x0000, and the command and response memory buffer
pointers are set to the base address of the buffers. If the device is configured to enter the active state, then the STATUS will
be 0x00 as shown in Table G-9.
Table G-30. After power up to the active state, the STATUS register contains:
If the device is configured to enter the sleep state, then the STATUS will be 0xFF at the completion of power. If the device is
configured to enter the standby state, then the STATUS will be 0xFF?? at the completion of power up – ChipState will remain
0xFFFF in the standby state.
Note:
Bit
Bit 0 (WIP)
Bit 1 (WEN)
Bit 2 (WAKEb)
Bit 3 (Reserved)
Bit 4 (CRCE)
Bit 5 (Reserved)
Bit 6 (RRDY)
Bit 7 (EERR)
•
•
Using the SPI RDSR command, or
Reading STATUS from address 0xFFF0
Reading the STATUS register after power up is completed will cause the device to WakeUp
Definition
“0b” indicates the device is ready, waiting for a command
"0b" indicates the device is not write enabled
"0b" indicates the device is not in the sleep or standby power state
Always "0b"
"0b" indicates no checksum error
Always "0b"
"0b" indicates the response memory buffer is empty
"0b" indicates no errors during execution
PU.RDY
), then the ATAES132 will enter the state specified by ChipConfig Register bits
Atmel ATAES132 Preliminary Datasheet
8760A−CRYPTO−5/11
102