ATAES132-SH-ER Atmel, ATAES132-SH-ER Datasheet - Page 122

• Manufacturer Part Number: ATAES132-SH-ER
• Description: EEPROM AES 32Kbit EE I2C
• Manufacturer: Atmel

Specifications of ATAES132-SH-ER

• Rohs: yes
• Maximum Clock Frequency: 1 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: I2C
• Factory Pack Quantity: 2300

Appendix J. I
J.1.
J.1.1.
J.1.2.
J.1.3.
J.1.4.
The ATAES132 two-wire serial interface is designed to interface directly to microcontrollers with I
interface and cleartext read/write operations operate similar to the Atmel I
The host sends ATAES132 extended commands to the device by writing the command packet to the command memory buffer
at address 0xFE00. The ATAES132 processes the command packet and places the response in the response memory buffer.
The host retrieves the response by reading the response packet from address 0xFE00.
See Section G.2 for additional information regarding the ATAES132 behavior in I
compatibility information.
I
When the ATAES132 is configured in I
standard-mode I
industry standard which is not formally documented or controlled. Multiple I
I
by the ATAES132.
The serial interface communication mode is selected by programming the I
described in Section E.2.15. The I
to I
I
The I
master is usually referred to as the Host or the Host microcontroller.
I
I
generate traffic on the I
always operates as a slave. In this specification the slave is usually referred to as the client or the device.
I
Each ATAES132 has a 7 bit I
by the Host to direct commands to a specific device on the I
matching I
cause the device to wakeup (See Appendix L for power management specifications).
The LSB of the I
high and a "write" operation is initiated if the R/W bit is low.
Relationship of Clock to Data
Data on the SDA pin may change only during SCK low time periods. Data changes during SCK high periods indicate an I
START or I
bus. The timing requirements for the clock and data signals are illustrated in Section J.7.
2
2
2
2
2
2
C slave must have a unique I
C slave devices receive the serial clock as an input, and receive instructions from the I
C Master
C Slave
C Device Address
C Serial Interface Description
2
C instructions which have a matching I
2
C master device generates the serial clock and sends instructions to the I
2
C device address. When the ATAES132 is in the standby state or sleep state, a matching I
2
C STOP condition. The SDA pin is pulled high by an external resistor when no devices are driving the I
2
C Interface
2
2
C slave device as described in this appendix. I
C device address byte is the read/write operation select bit – a "read" operation is initiated if the R/W bit is
2
C interface, slaves can only respond to instructions provided by the I
2
C device address (stored in the I
2
C device address to prevent bus contention. SCK clock frequencies up to 1MHz are supported
2
C device address is also located in the I
2
C serial communication mode, the serial interface operates as an I
2
C device address.
2
C interface. I
2
CAddr register, as described in Section E.2.15) which is used
2
C is a synchronous serial interface protocol that is a defacto
Atmel ATAES132 Preliminary Datasheet
2
2
C Serial EEPROM.
2
2
C devices will only respond to instructions with a
2
CAddr register. The ATAES132 will only respond
CAddr register in the configuration memory as
C devices can share the data bus; however, each
2
C slave devices. In this specification, the I
2
C interface mode. See Section J.6 for I
2
C master. I
2
C master. The ATAES132
2
C interface ports. The serial
2
C slaves can never
2
8760A−CRYPTO−5/11
C device address will
2
C compatible
2
C data
2
2
C
C
122
2
C