ATAES132-SH-ER Atmel, ATAES132-SH-ER Datasheet - Page 136

• Manufacturer Part Number: ATAES132-SH-ER
• Description: EEPROM AES 32Kbit EE I2C
• Manufacturer: Atmel

Specifications of ATAES132-SH-ER

• Rohs: yes
• Maximum Clock Frequency: 1 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: I2C
• Factory Pack Quantity: 2300

Table K-38. Device status register definition
The device status register can always be read, even if the the ATAES132 is processing a command or writing the EEPROM.
The SPI RDSR command is the preferred method for reading the STATUS in SPI interface mode.
If the ATAES132 is in the sleep or standby power state, reading the STATUS register forces the ATAES132 to wakeup – the
STATUS register is 0xFF until the wakeup process is complete.
Table K-39. Read status register bit definition using SPI RDSR command
Notes:
Bit
Bit 0 (WIP)
Bit 1 (WEN)
Bit 2 (WAKEb)
Bit 3 (Reserved)
Bit 4 (CRCE)
Bit 5 (Reserved)
Bit 6 (RRDY)
Bit 7 (EERR)
EERR
Bit 7
1.
2. STATUS register bits 0 - 7 are "1b"s during wakeup. During the first phase of wakeup (t
When the SPI RDSR command is used to read the STATUS register during an EEPROM write or during
execution of any ATAES132 command, then status bits 0 - 7 are "1b"s. The reserved bits will read as 0b if the
STATUS register is read directly from memory during an EEPROM write or during execution of an ATAES132
command.
tri-stated and any attempt to read it will be system-dependent. See for Appendix L additional information.
RRDY
Bit 6
Definition
“0b” indicates the device is ready, waiting for a command
“1b” indicates a write cycle or a cryptographic operation is in progress
"0b" indicates the device is not SPI write enabled
“1b” indicates the device is SPI write enabled
"0b" indicates the device is not in the sleep or standby power state
“1b” indicates the device is in the sleep or standby power state
Always "0b". This bit is reserved for future use.
"0b" indicates the most recent command block contained a correct checksum (CRC)
“1b” indicates the most recent command block contained an error
Always "0b". This bit is reserved for future use.
"0b" indicates the response memory buffer is empty
“1b” indicates the response memory buffer is ready to read
"0b" indicates the most recent command did not generate an error during execution
“1b” indicates the most recent command generated an execution error
Reserved
Bit 5
CRCE
Bit 4
Reserved
Bit 3
Atmel ATAES132 Preliminary Datasheet
(1)
(1)
(1)(2)
WAKEb
Bit 2
WEN
Bit 1
PU.STATUS
8760A−CRYPTO−5/11
), the SO pin is
Bit 0
WIP
136