ATAES132-SH-ER Atmel, ATAES132-SH-ER Datasheet - Page 81

• Manufacturer Part Number: ATAES132-SH-ER
• Description: EEPROM AES 32Kbit EE I2C
• Manufacturer: Atmel

Specifications of ATAES132-SH-ER

• Rohs: yes
• Maximum Clock Frequency: 1 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: I2C
• Factory Pack Quantity: 2300

D.2.2. Using the Command Memory Buffer
D.3.
D.3.2. Using the Response Memory Buffer
The host should write a single byte to the IO address reset register before writing a new command block to the command
memory buffer – this resets the buffer address pointer to the base address. The host then writes the ATAES132 command
block to the buffer using one or more standard SPI or I
host microcontroller, the ATAES132 checks the 16-bit checksum and executes the command. The host should read the
STATUS register to determine if an error occurred or if the response is ready to be read.
If a checksum error occurs, then the buffer address pointer must be reset by the host before the command block is
retransmitted. If no errors occur, then the response can be read from the response memory buffer as described in Section
D.3.2 (See Appendix G for examples).
The command memory buffer size is 64 bytes. If the host writes more than 64 bytes to the buffer, it will cause a buffer
overflow error. If the host hardware must send more bytes to the ATAES132 than are required to transmit a command block
(due to host hardware limitations), then all bytes transmitted after the block checksum must contain 0xFF.
Response Memory Buffer
The response memory buffer is a read-only memory buffer that is used by reading a response from the buffer at the base
address of 0xFE00. The base address of the response memory buffer contains the first byte of the response packet after a
crypto command is processed. See Section 6.1 for a description of the crypto response packet.
Read operations which begin at any location above the base address are invalid and will either be NAKed (in I
ignored (output will tri-state in SPI mode).
Table D-6.
The response memory buffer is also used to report errors that occur during execution of standard I
When the I
contains a block containing an error code (ReturnCode) if an error occurred, otherwise it contains a block containing
ReturnCode = 0x00. Reading the response memory buffer does not alter the contents of the response memory buffer or the
STATUS register (see Appendix G). See Section 6.3 for the error descriptions.
Table D-7.
After an ATAES132 command is executed, the RRDY bit of the STATUS register is set to 1b to indicate that a new response is
available in the response memory buffer. The host reads the response block from the buffer using one or more standard SPI
or I
If a checksum error occurs, then the buffer address pointer must be reset by the host before the response block is re-read. If
the host reads more bytes from the response buffer than necessary to retrieve the block, then all bytes after the block
checksum will contain 0xFF (See Appendix G for examples). The response memory buffer size is 64 bytes.
Address
Address
Count
Count
Base
Base
2
C read commands. After the entire response block is read, the host microcontroller checks the 16-bit checksum.
2
C or SPI command execution is complete (as indicated by the STATUS register), the response memory buffer
Response memory buffer map following a crypto command
Response memory buffer map following a standard I
ReturnCode
ReturnCode
Base
Base
+ 1
+ 1
Data1
CRC1
+ N-2
Base
Base
+ 2
Data2
CRC2
+ N-1
Base
Base
+ 3
2
C write commands. After the entire command block is written by the
Data3
......
......
FF
h
2
C or SPI write operation
.......
......
......
FF
h
Atmel ATAES132 Preliminary Datasheet
.......
......
......
FF
h
DataX
......
......
FF
h
2
C or SPI write commands.
8760A−CRYPTO−5/11
CRC1
+ N-2
Base
......
FF
h
2
C mode) or be
CRC2
+ N-1
Base
......
FF
h
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