ATAES132-SH-ER Atmel, ATAES132-SH-ER Datasheet - Page 162

• Manufacturer Part Number: ATAES132-SH-ER
• Description: EEPROM AES 32Kbit EE I2C
• Manufacturer: Atmel

Specifications of ATAES132-SH-ER

• Rohs: yes
• Maximum Clock Frequency: 1 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: I2C
• Factory Pack Quantity: 2300

R.1.5. SPI Write Enable Changed by Illegal Read
R.1.6. I
R.1.7. I
R.1.8. I
R.1.9. EncWrite to Key Memory
R.1.10. EERR Status bit Reset by Memory Read
R.1.11. EERR Status bit Incorrect for Memory Read Beyond End of User Memory
If an SPI Read is executed after the write enable flag is enabled, the write enable flag should not change. Actual behavior is
an SPI read of an illegal address causes the write enable flag to change to the disabled state. The flag is not changed by SPI
reads of legal addresses.
This problem will be fixed in future revisions of ATAES132.
If a standard I
first byte returned should be the byte following the last byte clocked in by the write command. Actual behavior is the internal
address register used by the standard I
operation is performed, therefore, the I
This problem will be fixed in future revisions of ATAES132.
In the I
I
the I
This problem will be fixed in future revisions of ATAES132.
The minimum I
Hold time.
This problem will be fixed in future revisions of ATAES132.
The EncWrite command should permit key memory to be written using encrypted data as described in Section 7.11. Actual
behavior is that the EncWrite command appears to function correctly when writing to key memory, however, the new contents
of the key register will be incorrect. Since the new key value is unknown, all operations with the key will generate incorrect
cryptographic results.
It is recommended that the key memory be written with cleartext using the standard write commands as described in Section
5.3.3 prior to locking key memory. The key memory can be updated after locking using the KeyCompute command or the
KeyLoad command if the key is configured as a child key in the KeyConfig register.
This problem will be fixed in future revisions of ATAES132.
If a SPI or I
Once set, the EERR status bit should retain the 1bs state during the read operation, regardless of how much data is read.
Actual behavior is that the EERR bit will be set to 0b on the 129th byte read, causing the error information to be lost.
This problem will be fixed in future revisions of ATAES132.
If a SPI or I
should be set to 1b and 0xFF should be returned for each data byte. Actual behavior is 0xFF is returned for each data byte
above address 0x0FFF, however, the EERR bit is 0b.
This problem will be fixed in future revisions of ATAES132.
2
2
2
2
CAddr register. Actual behavior is the ATAES132 ACKs an I
C Current Address Read
C Device Address
C Data In Hold Time
2
CAddr register.
2
C interface mode, the device should only ACK the device address if all seven bits match the value stored in the
2
2
C read begins at an authorized address and continues into protected memory, the EERR bit will be set to 1b.
C read begins at an authorized user memory address and continues beyond address 0x0FFF, the EERR bit
2
C current address read operation is performed after a standard I
2
C data in Hold time specification is 0ns. This revision of the ATAES132 requires 10ns minimum I
2
2
C current address read does not return the expected bytes.
C read operations is not updated when a standard I
2
C address in which only the upper six bits match the value in
Atmel ATAES132 Preliminary Datasheet
2
C byte write or I
2
C byte write or I
2
C page write operation, the
8760A−CRYPTO−5/11
2
C page write
2
C dataiIn
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