ATAES132-SH-ER Atmel, ATAES132-SH-ER Datasheet - Page 89

• Manufacturer Part Number: ATAES132-SH-ER
• Description: EEPROM AES 32Kbit EE I2C
• Manufacturer: Atmel

Specifications of ATAES132-SH-ER

• Rohs: yes
• Maximum Clock Frequency: 1 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: I2C
• Factory Pack Quantity: 2300

E.2.20. CounterConfig Registers
E.2.21. KeyConfig Registers
The 16 CounterConfig registers are used to individually configure the 16 Counters. Each CounterConfig register controls one
counter. CounterConfig 00 controls Counter 00, CounterConfig 01 controls Counter 01, etc.
Each CounterConfig register is a two byte array which is stored as shown in Table E-8. The customer can write the
CounterConfig registers with the standard I
the LockConfig register definition in Section E.2.11). See Appendix H for additional counter information.
Table E-15. Partial configuration memory map showing CounterConfig register byte locations for four registers
The CounterConfig register imposes restrictions on the usage of the counter command (see Section 7.5) with a counter. The
CounterConfig bits have no impact on the functionality of a key usage counter. If a counter is identified in a KeyConfig register
(see Section E.2.21) as a Key Usage Counter, then the counter will increment each time the key is used. The
CounterConfig[CntID].IncrementOK is typically set to 0b to prohibit the counter command from incrementing a key usage
counter.
Table E-16. Definition of the CounterConfig register bits
Note:
The 16 KeyConfig registers are used to individually configure the 16 keys. Each KeyConfig register controls one key.
KeyConfig 00 controls Key 00, KeyConfig 01 controls Key 01, etc.
Each KeyConfig register is a four byte array which is stored as shown in Table E-10. The customer can write the KeyConfig
registers with the standard I
register definition in Section E.2.11).
Table E-17. Partial configuration memory map showing KeyConfig register byte locations for two registers
Address
F060
CounterConfig Field
IncrementOK
RequireMAC
Reserved
IncrID
MacID
Address
F080
h
h
-F067
-F087
1. Changes to the CounterConfig registers take effect immediately, which allow the functionality to be verified
h
h
during the personalization process
Byte 0
Byte 0
CounterConfig 0
0
0
h
h
Byte
0
0
0
1
1
2
C or SPI write commands unless the Configuration Memory has been locked (see the LockConfig
Byte 1
Byte 1
1
2 to 7
0 to 3
1
4 to7
h
h
Bit
KeyConfig 0
0
1
2
C or SPI write commands unless the configuration memory has been locked (see
Description
If 1b, then increments using the Counter command are permitted
If 0b, then increments using the Counter command are prohibited
If 1b, then the increment operation requires an input MAC
If 0b, then an input MAC is prohibited
Reserved for future use. All bits must be 0b
KeyID of the key used to generate the Counter command input MAC for
increment operations
KeyID of the key used to generate the Counter command output MAC for
counter read operations
Byte 0
Byte 2
CounterConfig 1
2
2
h
h
(1)
Byte 1
Byte 3
3
3
h
h
Atmel ATAES132 Preliminary Datasheet
Byte 0
Byte 0
CounterConfig 2
4
4
h
h
Byte 1
Byte 1
5
5
h
h
KeyConfig 1
Byte 0
Byte 2
8760A−CRYPTO−5/11
CounterConfig 3
6
6
h
h
Byte 1
Byte 3
7
7
h
h
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