IS42S16400F-6TL ISSI, Integrated Silicon Solution Inc, IS42S16400F-6TL Datasheet

IC SDRAM 64MBIT 166MHZ 54TSOP

IS42S16400F-6TL

Manufacturer Part Number
IS42S16400F-6TL
Description
IC SDRAM 64MBIT 166MHZ 54TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheets

Specifications of IS42S16400F-6TL

Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (4M x 16)
Speed
166MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Organization
4Mx16
Density
64Mb
Address Bus
14b
Access Time (max)
6/5.4ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
130mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Data Bus Width
16 bit
Maximum Clock Frequency
166 MHz
Access Time
6 ns, 5.4 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
130 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
706-1075
IS42S16400F-6TL

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IS42S16400F
IC42S16400F
FEATURES
• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
• Programmable burst sequence:
• Self refresh modes
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
• Burst termination by burst stop and precharge
• Byte controlled by LDQM and UDQM
• Package: 400-mil 54-pin TSOP II
• Lead-free package is available
• Available in Industrial Temperature
• Please contact Product Manager for informa-
PIN DESCRIPTIONS
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
03/19/08
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
A0-A11
BA0, BA1
DQ0 to DQ15
CLK
CKE
CS
RAS
CAS
positive clock edge
– (1, 2, 4, 8, full page)
Sequential/Interleave
operations capability
command
tion on mobile functions (Power Down and Deep
Power Down Mode, Partial Array Self Refresh,
Temperature Compensated Self Refresh, Output
Driver Strength Selection)
Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
OVERVIEW
ISSI
IC42S16400F are organized as 1,048,576 bits x 16-bit x
4-bank for improved performance.ThesynchronousDRAMs
achieve high-speed data transfer using pipeline architecture.
All inputs and outputs signals refer to the rising edge of
the clock input.
PIN CONFIGURATIONS
54-Pin TSOP (Type II)
WE
LDQM
UDQM
V
GND
V
GND
NC
DD
DD
's 64Mb Synchronous DRAM IS42S16400F and
q
q
GNDQ
GNDQ
VDDQ
VDDQ
LDQM
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VDD
CAS
RAS
VDD
BA0
BA1
A10
WE
CS
A0
A1
A2
A3
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for DQ Pin
Ground for DQ Pin
No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
March 2008
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
GND
DQ15
GNDQ
DQ14
DQ13
VDDQ
DQ12
DQ11
GNDQ
DQ10
DQ9
VDDQ
DQ8
GND
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
GND
1

IS42S16400F-6TL Summary of contents

Page 1

... Integrated Silicon Solution, Inc. — www.issi.com Rev. A 03/19/08 March 2008 OVERVIEW ISSI 's 64Mb Synchronous DRAM IS42S16400F and IC42S16400F are organized as 1,048,576 bits x 16-bit x 4-bank for improved performance.ThesynchronousDRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. ...

Page 2

... IS42S16400F IC42S16400F GENERAL DESCRIPTION The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits. The 64Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode ...

Page 3

... IS42S16400F IC42S16400F PIN FUNCTIONS Symbol TSOP Pin No. Type A0-A11 Input Pin 22, 35 BA0, BA1 20, 21 Input Pin CAS 17 Input Pin CKE 37 Input Pin CLK 38 Input Pin CS 19 Input Pin DQ0 10, DQ Pin DQ15 11,13, 42, 44, 45, 47, 48, 50, 51, 53 LDQM, 15, 39 Input Pin ...

Page 4

... IS42S16400F IC42S16400F FUNCTION (In Detail) A0-A11 are address inputs sampled during the ACTIVE (row-address A0-A11) and READ/WRITE command (A0-A7 with A10 defining auto PRECHARGE). A10 is sampled during a PRECHARGE command to determine if all banks are to be PRECHARGED (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command ...

Page 5

... IS42S16400F IC42S16400F AUTO PRECHARGE does not apply except in full-page burst mode. Upon completion of the READ or WRITE burst, a precharge of the bank/row that is addressed is automatically performed. AUTO REFRESH COMMAND This command executes the AUTO REFRESH operation. The row address and bank to be refreshed are automatically generatedduringthisoperation ...

Page 6

... IS42S16400F IC42S16400F TRUTH TABLE – COMMANDS AND DQM OPERATION FUNCTION COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank/column, start READ burst) WRITE (Select bank/column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH ...

Page 7

... IS42S16400F IC42S16400F TRUTH TABLE – CKE (1-4) CURRENT STATE COMMANDn Power-Down X Self Refresh X Clock Suspend X Power-Down COMMAND INHIBIT or NOP (5) Self Refresh (6) COMMAND INHIBIT or NOP Clock Suspend X (7) All Banks Idle COMMAND INHIBIT or NOP All Banks Idle AUTO REFRESH Reading or Writing VALID See TRUTH TABLE – ...

Page 8

... IS42S16400F IC42S16400F 3. Current state definitions: Idle: The bank has been precharged, and t Row Active: A row in the bank has been activated, and t accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi- nated ...

Page 9

... IS42S16400F IC42S16400F TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK m CURRENT STATE COMMAND (ACTION) Any COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) Idle Any Command Otherwise Allowed to Bank m Row ACTIVE (Select and activate row) Activating, READ (Select column and start READ burst) ...

Page 10

... IS42S16400F IC42S16400F 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been inter- rupted by bank m’s burst. 9. Burst in bank n continues as initiated. 10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later (Consecutive READ Bursts) ...

Page 11

... IS42S16400F IC42S16400F ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage DD max V Maximum Supply Voltage for Output Buffer DDq max V Input Voltage iN V Output Voltage out P Allowable Power Dissipation D max I output Shorted Current cs T operating Temperature opr T Storage Temperature stg DC RECOMMENDED OPERATING CONDITIONS ...

Page 12

... IS42S16400F IC42S16400F DC ELECTRICAL CHARACTERISTICS Symbol Parameter i Input Leakage Current il i Output Leakage Current ol V Output High Voltage Level oh V Output Low Voltage Level ol i Operating Current (1,2) cc1 i Precharge Standby Current cc2p I (In Power-Down Mode) cc2ps i Precharge Standby Current (3) cc2N I (In Non Power-Down Mode) ...

Page 13

... IS42S16400F IC42S16400F AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Clock Cycle Time ck3 t ck2 t Access Time From CLK (4,6) ac3 t ac2 t CLK HIGH Level Width chi t CLK LOW Level Width cl t Output Data Hold Time (6) oh3 t oh2 t Output LOW Impedance Time lz t Output HIGH Impedance Time ...

Page 14

... IS42S16400F IC42S16400F OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency t READ/WRITE command to READ/WRITE command ccD t CKE to clock disable or power-down entry mode ckeD t CKE to clock enable or power-down exit setup mode peD t DQM to input data delay DqD t DQM to data mask during WRITEs ...

Page 15

... IS42S16400F IC42S16400F FUNCTIONAL DESCRIPTION The 64Mb SDRAMs (1 Meg banks) are quad-bank DRAMs which operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. ...

Page 16

... IS42S16400F IC42S16400F REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power ...

Page 17

... IS42S16400F IC42S16400F Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length deter- mines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst ...

Page 18

... IS42S16400F IC42S16400F CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge ...

Page 19

... IS42S16400F IC42S16400F OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). ...

Page 20

... IS42S16400F IC42S16400F READS READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst ...

Page 21

... IS42S16400F IC42S16400F diagram for each possible CAS latency; data element either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until t is met. Note that part of the row precharge time is rp hidden during the access of the last data element(s) ...

Page 22

... IS42S16400F IC42S16400F Consecutive READ Bursts T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - NOP NOP NOP READ BANK, COL n+1 D OUT OUT NOP NOP READ BANK, COL n+1 OUT OUT Integrated Silicon Solution, Inc. — ...

Page 23

... IS42S16400F IC42S16400F Random READ Accesses T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 03/19/ READ READ READ BANK, BANK, BANK, COL b COL m COL OUT OUT CAS Latency - 2 ...

Page 24

... IS42S16400F IC42S16400F RW1 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 2 RW2 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL NOP NOP NOP NOP n+1 D n+2 OUT OUT OUT NOP NOP NOP OUT CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com ...

Page 25

... IS42S16400F IC42S16400F READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 03/19/ NOP NOP NOP PRECHARGE cycle BANK (a or all) ...

Page 26

... IS42S16400F IC42S16400F READ Burst Termination T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - BURST NOP NOP NOP TERMINATE n+1 D OUT OUT BURST NOP NOP TERMINATE cycles n+1 OUT OUT Integrated Silicon Solution, Inc. — www.issi.com ...

Page 27

... IS42S16400F IC42S16400F WRITEs WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram. WRITE Command CLK HIGH - Z CKE CS RAS CAS WE A0-A7 COLUMN ADDRESS A8, A9, A11 AUTO PRECHARGE A10 NO PRECHARGE BA0, BA1 BANK ADDRESS The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access ...

Page 28

... IS42S16400F IC42S16400F WRITE Burst CLK COMMAND ADDRESS WRITE to WRITE COMMAND Random WRITE Cycles COMMAND ADDRESS WRITE NOP NOP BANK, COL n CLK WRITE NOP BANK, ADDRESS COL n DON'T CARE CLK WRITE WRITE WRITE BANK, BANK, BANK, COL n COL b COL Integrated Silicon Solution, Inc. — www.issi.com ...

Page 29

... IS42S16400F IC42S16400F WRITE to READ T0 CLK COMMAND WRITE BANK, ADDRESS COL WP1 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL Integrated Silicon Solution, Inc. — www.issi.com Rev. A 03/19/ NOP READ NOP BANK, COL n+1 IN CAS Latency - NOP NOP ACTIVE PRECHARGE BANK ...

Page 30

... IS42S16400F IC42S16400F WP2 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS NOP NOP NOP PRECHARGE BANK (a or all n+1 IN CAS Latency - CLK BURST WRITE TERMINATE BANK, (ADDRESS) COL DON'T CARE Integrated Silicon Solution, Inc. — www.issi.com ...

Page 31

... IS42S16400F IC42S16400F PRECHARGE The PRECHARGE command (see figure) is used to deac- tivate the open row in a particular bank or the open row in all banks.The bank(s) will be available for a subsequent row access some specified time (t ) after the PRECHARGE rp command is issued. Input A10 determines whether one or ...

Page 32

... IS42S16400F IC42S16400F CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. ...

Page 33

... IS42S16400F IC42S16400F BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access ...

Page 34

... IS42S16400F IC42S16400F WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after t is met, where t begins when the READ to bank registered ...

Page 35

... IS42S16400F IC42S16400F INITIALIzE AND LOAD MODE REGISTER CLK CKS CKH CKE CMH CMS CMH CMS COMMAND NOP PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 ALL BANKS Power-up: V Precharge CC and CLK stable all banks T = 100µs Min. ...

Page 36

... IS42S16400F IC42S16400F POWER-DOWN MODE CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Two clock cycles Precharge all All banks idle, enter active banks power-down mode ...

Page 37

... IS42S16400F IC42S16400F CLOCK SUSPEND MODE CLK CKS CKH CKS CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM/ DQML, DQMH A0-A9, A11 COLUMN m ( A10 BA0, BA1 BANK DQ Notes: 1. CAS latency = 3, burst length = and A = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com Rev ...

Page 38

... IS42S16400F IC42S16400F AUTO-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE NOP DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High-Z t CAS latency = Auto NOP Refresh Integrated Silicon Solution, Inc. — www.issi.com Tn+1 ...

Page 39

... IS42S16400F IC42S16400F SELF-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE NOP DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High Precharge all active banks refresh mode CAS latency = 2, 3 Integrated Silicon Solution, Inc. — www.issi.com Rev ...

Page 40

... IS42S16400F IC42S16400F READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. CAS latency = 2, burst length = 4 2 ...

Page 41

... IS42S16400F IC42S16400F READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. CAS latency = 2, burst length = and A = "Don't Care" ...

Page 42

... IS42S16400F IC42S16400F SINGLE READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. CAS latency = 2, burst length = 1 2 ...

Page 43

... IS42S16400F IC42S16400F SINGLE READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. CAS latency = 2, burst length = and A = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com Rev ...

Page 44

... IS42S16400F IC42S16400F ALTERNATING BANK READ ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK 0 RCD t RRD t - BANK 0 RAS t - BANK 0 RC Notes: 1. CAS latency = 2, burst length = 4 2 ...

Page 45

... IS42S16400F IC42S16400F READ - FULL-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP READ t CMS DQM/ DQML, DQMH A0-A9, A11 ROW COLUMN A10 ROW BA0, BA1 BANK BANK DQ t RCD Notes: 1. CAS latency = 2, burst length = full page and A = "Don't Care" ...

Page 46

... IS42S16400F IC42S16400F READ - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD Notes: 1. CAS latency = 2, burst length = 4 2 ...

Page 47

... IS42S16400F IC42S16400F WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. burst length = and A = "Don't Care" ...

Page 48

... IS42S16400F IC42S16400F WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK RCD t RAS t RC Notes: 1. burst length = and A = "Don't Care" WRITE ...

Page 49

... IS42S16400F IC42S16400F SINGLE WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. burst length = and A = " ...

Page 50

... IS42S16400F IC42S16400F SINGLE WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND (3) ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. burst length = and A = "Don't Care" (3) (3) NOP NOP ...

Page 51

... IS42S16400F IC42S16400F ALTERNATING BANK WRITE ACCESS CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMH A0-A9, A11 ROW COLUMN ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK 0 RCD t RRD t - BANK 0 RAS t - BANK 0 RC Notes: 1. burst length = 4 2 ...

Page 52

... IS42S16400F IC42S16400F WRITE - FULL PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1. burst length = full page and A = "Don't Care" WRITE NOP NOP t t CMS ...

Page 53

... IS42S16400F IC42S16400F WRITE - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1. burst length = and A = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com Rev. A ...

Page 54

... TSOP II, Lead-free IS42S16400F-6TL 400-mil TSOP II, Lead-free IC42S16400F-6TL 400-mil TSOP II, Lead-free IS42S16400F-7TL 400-mil TSOP II, Lead-free IC42S16400F-7TL 400-mil TSOP II, Lead-free Order Part No. Package IS42S16400F-5TLI 400-mil TSOP II, Lead-free IS42S16400F-6TLI 400-mil TSOP II, Lead-free IS42S16400F-7TLI 400-mil TSOP II, Lead-free Integrated Silicon Solution, Inc. — www.issi.com Rev. A 03/19/08 ...

Page 55

PACKAGING INFORMATION Plastic TSOP 54–Pin, 86-Pin Package Code: T (Type II Plastic TSOP (T - Type II) Millimeters Symbol Min Max Ref. Std. 54 No. Leads (N) A — 1.20 — A1 0.05 0.15 A2 ...

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