HUF76639S3ST_F085 Fairchild Semiconductor, HUF76639S3ST_F085 Datasheet - Page 8

• Manufacturer Part Number: HUF76639S3ST_F085
• Description: MOSFET 50A, 100V, 0.026 Ohm N-Channel UltraFET
• Manufacturer: Fairchild Semiconductor

Specifications of HUF76639S3ST_F085

• Rohs: yes
• Transistor Polarity: N-Channel
• Drain-source Breakdown Voltage: 100 V
• Continuous Drain Current: 50 A
• Resistance Drain-source Rds (on): 0.026 Ohms
• Maximum Operating Temperature: + 175 C
• Mounting Style: SMD/SMT
• Package / Case: TO-263AB
• Fall Time: 136 ns
• Gate Charge Qg: 86 nC
• Minimum Operating Temperature: - 55 C
• Power Dissipation: 180 W
• Rise Time: 207 ns
• Typical Turn-off Delay Time: 83 ns

SABER Electrical Model
REV 26 July 1999
template huf76639 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 2.6e-12, cjo = 2.1e-9, tt = 5.6e-8, m = 0.52, n=10)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 2.6e-9, is = 1e-30, m = 0.89)
m..model mmedmod = (type=_n, vto = 1.77, kp = 7, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.06,kp = 95, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.48, kp = 0.12,is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.5, voff = -2.0)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -2.0, voff = -4.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.3)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.3, voff = -0.5)
c.ca n12 n8 = 4.2e-9
c.cb n15 n14 = 4.2e-9
c.cin n6 n8 = 2.27e-9
d.dbody n7 n71 = model = dbodymod
d.dbreak n72 n11 = model = dbreakmod
d.dplcap n10 n5 = model = dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1.0e-9
l.lgate n1 n9 = 5.1e-9
l.lsource n3 n7 = 3.1e-9
m.mmed n16 n6 n8 n8 = model = mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model = mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model = mweakmod, l = 1u, w = 1u
res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -5e-7
res.rdbody n71 n5 = 2.65e-3, tc1 = 1.5e-3, tc2 = 3.5e-6
res.rdbreak n72 n5 = 2.5e-1, tc1 = 1e-4, tc2 = -1e-6
res.rdrain n50 n16 = 15.8e-3, tc1 = 8.5e-3, tc2 = 2.3e-5
res.rgate n9 n20 = 1.94
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 51
res.rlsource n3 n7 = 31
res.rslc1 n5 n51 = 1e-6, tc1 = 3.4e-3, tc2 = 2.5e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.6e-3, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.7e-3, tc2 = 1.5e-6
res.rvthres n22 n8 = 1, tc1 = -1.9e-3, tc2 = -4.5e-6
spe.ebreak n11 n7 n17 n18 = 118.2
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model = s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model = s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model = s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model = s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/99))** 3.5))
}
}
©2012 Fairchild Semiconductor Corporation
GATE
1
RLGATE
LGATE
9
RGATE
CA
12
20
EVTEMP
+
S1A
S1B
ESG
18
22
EGS
13
8
+
-
-
13
6
8
10
+
+
-
-
14
13
6
8
6
RSLC2
S2A
S2B
DPLCAP
EVTHRES
+
EDS
19
8
15
CB
CIN
-
+
-
5
8
5
MSTRO
14
51
21
RDRAIN
RSLC1
50
ISCL
16
8
MMED
8
RDBREAK
DBREAK
IT
RSOURCE
MWEAK
17
EBREAK
RVTHRES
RBREAK
72
11
+
-
17
18
7
+
-
18
22
RVTEMP
19
HUF76639S3ST_F085 Rev. C1
71
RLSOURCE
LSOURCE
VBAT
RLDRAIN
RDBODY
DBODY
LDRAIN
SOURCE
DRAIN
2
3