ADP5585CP-EVALZ Analog Devices, ADP5585CP-EVALZ Datasheet - Page 4

• Manufacturer Part Number: ADP5585CP-EVALZ
• Description: Interface Development Tools LFCSP Evaluation Board
• Manufacturer: Analog Devices
• Series: ADP5585r

Specifications of ADP5585CP-EVALZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: ADP5585
• Interface Type: I2C
• Operating Supply Voltage: 1.8 V to 3 V
• Factory Pack Quantity: 1

ADP5585
Parameter
I
1
2
3
4
TIMING DIAGRAM
2
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at T
Guaranteed by design.
All timers are referenced from the base oscillator and have the same ±10% accuracy.
C
C TIMING SPECIFICATIONS
B
Delay from UVLO/Reset Inactive to I
SCL Clock Frequency
SCL High Time
SCL Low Time
Data Setup Time
Data Hold Time
Setup Time for Repeated Start
Hold Time for Start/Repeated Start
Bus Free Time for Stop and Start Condition
Setup Time for Stop Condition
Data Valid Time
Data Valid Acknowledge
Rise Time for SCL and SDA
Fall Time for SCL and SDA
Pulse Width of Suppressed Spike
Capacitive Load for Each Bus Line
is the total capacitance of one bus line in picofarads.
V
V
IL
IH
= 0.3VDD
= 0.7VDD
SDA
SDA
SCL
SCL
t
SU; STA
70%
30%
S
t
F
t
F
FIRST CLOCK CYCLE
70%
30%
Sr
t
HD; STA
2
C Access
1/
t
R
t
f
HD; DAT
SCL
t
HD; STA
70%
30%
70%
30%
Symbol
t
f
t
t
t
t
t
t
t
t
t
t
t
t
C
t
SCL
HIGH
LOW
SU; DAT
HD; DAT
SU; STA
HD; STA
BUF
SU; STO
VD; DAT
VD; ACK
R
F
SP
SP
B
t
4
Figure 2. I
SU; DAT
Rev. C | Page 4 of 40
2
C Interface Timing Diagram
Test Conditions/Comments
t
R
70%
30%
70%
30%
t
NINTH CLOCK
t
VD; ACK
LOW
t
SU; STO
t
HIGH
70%
30%
t
VD; DAT
P
t
BUF
S
Min
0
0.26
0.5
50
0
0.26
0.26
0.5
0.26
0
NINTH CLOCK
A
= 25°C, VDD = 1.8 V.
Typ
Data Sheet
Max
60
1000
0.45
0.45
120
120
50
550
Unit
μs
kHz
μs
μs
ns
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
pF