MT48LC64M8A2P-75:C Micron Technology Inc, MT48LC64M8A2P-75:C Datasheet - Page 22
![IC SDRAM 512MBIT 133MHZ 54TSOP](/photos/7/22/72261/557-54-tsop_sml.jpg)
MT48LC64M8A2P-75:C
Manufacturer Part Number
MT48LC64M8A2P-75:C
Description
IC SDRAM 512MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC64M8A2TG-75C_TR.pdf
(68 pages)
Specifications of MT48LC64M8A2P-75:C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (64M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Organization
64Mx8
Density
512Mb
Address Bus
15b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
115mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC64M8A2P-75:C
Manufacturer:
MITSUBISHI
Quantity:
450
Figure 10:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
CAS Latency
COMMAND
COMMAND
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z. A full-page burst will continue until terminated (at the end of the page, it
will wrap to the start address and continue). Data from any READ burst may be trun-
cated with a subsequent READ command, and data from a fixed-length READ burst may
be immediately followed by data from a READ command.
In either case, a continuous flow of data can be maintained. The first data element from
the new burst either follows the last element of a completed burst or the last desired data
element of a longer burst that is being truncated. The new READ command should be
issued x cycles before the clock edge at which the last desired data element is valid,
where x = CL - 1. This is shown in Figure 10 for CL = 2 and CL = 3; data element n + 3 is
either the last of a burst of four or the last desired of a longer burst.
The 512Mb SDRAM uses a pipelined architecture and therefore does not require the 2n
rule associated with a prefetch architecture. A READ command can be initiated on any
clock cycle following a previous READ command. Full-speed random read accesses can
be performed to the same bank, as shown in Figure 12 on page 24, or each subsequent
READ may be performed to a different bank.
CLK
CLK
DQ
DQ
READ
READ
T0
T0
CL = 2
NOP
NOP
T1
T1
22
t
t AC
LZ
CL = 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
NOP
T2
NOP
t
t AC
LZ
D
t OH
OUT
512Mb: x4, x8, x16 SDRAM
T3
T3
NOP
D
t OH
OUT
Don’t Care
Undefined
©2000 Micron Technology, Inc. All rights reserved.
T4
Operations