MT48LC64M8A2P-75:C Micron Technology Inc, MT48LC64M8A2P-75:C Datasheet - Page 25
![IC SDRAM 512MBIT 133MHZ 54TSOP](/photos/7/22/72261/557-54-tsop_sml.jpg)
MT48LC64M8A2P-75:C
Manufacturer Part Number
MT48LC64M8A2P-75:C
Description
IC SDRAM 512MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC64M8A2TG-75C_TR.pdf
(68 pages)
Specifications of MT48LC64M8A2P-75:C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (64M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Organization
64Mx8
Density
512Mb
Address Bus
15b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
115mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC64M8A2P-75:C
Manufacturer:
MITSUBISHI
Quantity:
450
Figure 13:
Figure 14:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
READ-to-WRITE
READ-to-WRITE with Extra Clock Cycle
Note:
Note:
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 13
shows the case where the clock frequency allows for bus contention to be avoided
without adding a NOP cycle, and Figure 14 shows the case where the additional NOP is
needed.
COMMAND
COMMAND
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE
command to the same bank (provided that auto precharge was not activated), and a full-
page burst may be truncated with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before the clock edge at which the last
desired data element is valid, where x = CL - 1. This is shown in Figure 15 on page 26 for
ADDRESS
ADDRESS
A CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE
command may be to any bank. If a burst of 1 is used, then DQM is not required.
CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE
command may be to any bank.
DQM
DQM
CLK
CLK
DQ
DQ
BANK,
T0
COL n
BANK,
COL n
READ
T0
READ
T1
T1
NOP
NOP
Transitioning Data
25
T2
T2
NOP
NOP
Transitioning Data
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
NOP
D
NOP
OUT
t
t HZ
D
HZ
t
n
OUT
CK
n
Don’t Care
BANK,
T4
COL b
WRITE
T4
NOP
D
IN
b
t
512Mb: x4, x8, x16 SDRAM
DS
Don’t Care
T5
BANK,
COL b
WRITE
D
IN
b
t
©2000 Micron Technology, Inc. All rights reserved.
DS
Operations