MT48LC64M8A2P-75:C Micron Technology Inc, MT48LC64M8A2P-75:C Datasheet - Page 57
![IC SDRAM 512MBIT 133MHZ 54TSOP](/photos/7/22/72261/557-54-tsop_sml.jpg)
MT48LC64M8A2P-75:C
Manufacturer Part Number
MT48LC64M8A2P-75:C
Description
IC SDRAM 512MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC64M8A2TG-75C_TR.pdf
(68 pages)
Specifications of MT48LC64M8A2P-75:C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (64M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Organization
64Mx8
Density
512Mb
Address Bus
15b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
115mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC64M8A2P-75:C
Manufacturer:
MITSUBISHI
Quantity:
450
Figure 41:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
DQML, DQMH
COMMAND
A0–A9, A12
BA0, BA1
DQM/
CLK
CKE
A10
DQ
t CKS
t CMS
t AS
t AS
t AS
Single READ – With Auto Precharge
ACTIVE
T0
ROW
ROW
BANK
t CMH
t CKH
t AH
t AH
t AH
Notes:
t RCD
t RAS
t RC
t CK
T1
1. For this example, BL = 1, and CL = 2.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
3. READ command is not allowed else
NOP
t CL
T2
NOP 3
t CH
T3
NOP 3
ENABLE AUTO PRECHARGE
t CMS
57
COLUMN m 2
BANK
T4
READ
t CMH
CAS Latency
t
RAS would be violated.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T5
NOP
t AC
t RP
D
T6
512Mb: x4, x8, x16 SDRAM
OUT
NOP
t OH
m
t HZ
©2000 Micron Technology, Inc. All rights reserved.
ACTIVE
BANK
ROW
T7
ROW
Timing Diagrams
T8
NOP
Don’t Care
Undefined