MT48LC64M8A2P-75:C Micron Technology Inc, MT48LC64M8A2P-75:C Datasheet - Page 35
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MT48LC64M8A2P-75:C
Manufacturer Part Number
MT48LC64M8A2P-75:C
Description
IC SDRAM 512MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC64M8A2TG-75C_TR.pdf
(68 pages)
Specifications of MT48LC64M8A2P-75:C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (64M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Organization
64Mx8
Density
512Mb
Address Bus
15b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
115mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC64M8A2P-75:C
Manufacturer:
MITSUBISHI
Quantity:
450
Concurrent Auto Precharge
READ with Auto Precharge
Figure 28:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
Internal
States
READ with Auto Precharge Interrupted by a READ
COMMAND
Note:
ADDRESS
BANK m
BANK n
CLK
An access command to (READ or WRITE) another bank while an access command with
auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM
supports concurrent auto precharge. Micron SDRAMs support concurrent auto
precharge. Four cases where concurrent auto precharge occurs are defined below.
• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
DQ
rupt a READ on bank n, CL later. The PRECHARGE to bank n will begin when the
READ to bank m is registered (see Figure 28).
interrupt a READ on bank n when registered. DQM should be used two clocks prior to
the WRITE command to prevent bus contention. The PRECHARGE to bank n will
begin when the WRITE to bank m is registered (see Figure 29 on page 36).
DQM is LOW.
Page Active
T0
NOP
READ - AP
BANK n,
Page Active
BANK n
COL a
T1
READ with Burst of 4
CL = 3 (BANK n)
T2
NOP
35
BANK m,
READ - AP
T3
BANK m
COL d
Interrupt Burst, Precharge
READ with Burst of 4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T4
CL = 3 (BANK m)
NOP
D
OUT
a
t
RP - BANK n
Transitioning Data
T5
NOP
D
a + 1
512Mb: x4, x8, x16 SDRAM
OUT
T6
NOP
D
©2000 Micron Technology, Inc. All rights reserved.
OUT
d
Idle
Don’t Care
T7
NOP
t RP - BANK m
Precharge
D
d + 1
OUT
Operations