MT48LC64M8A2P-75:C Micron Technology Inc, MT48LC64M8A2P-75:C Datasheet - Page 48
![IC SDRAM 512MBIT 133MHZ 54TSOP](/photos/7/22/72261/557-54-tsop_sml.jpg)
MT48LC64M8A2P-75:C
Manufacturer Part Number
MT48LC64M8A2P-75:C
Description
IC SDRAM 512MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC64M8A2TG-75C_TR.pdf
(68 pages)
Specifications of MT48LC64M8A2P-75:C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (64M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Organization
64Mx8
Density
512Mb
Address Bus
15b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
115mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC64M8A2P-75:C
Manufacturer:
MITSUBISHI
Quantity:
450
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
22. V
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
24. Auto precharge mode only. The precharge timing budget (
25. Precharge mode only.
26. JEDEC and PC100, PC133 specify three clocks.
27.
28. Parameter guaranteed by design.
29. For -75, CL = 3,
30. CKE is HIGH during refresh command period
cannot be greater than one-third of the cycle rate. V
a pulse width ≤ 3ns for all inputs. V
a pulse width ≤ 3ns, and the pulse width cannot be greater than one-third of the cycle
rate.
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including
used to reduce the data rate.
the first clock delay, after the last WRITE is executed.
t
limit is actually a nominal value and does not result in a fail value.
AC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design.
IH
overshoot: V
t
CK = 7.5ns; for -7E, CL = 2,
IH
(MAX) = V
48
DD
Q + 2V for a pulse width ≤ 3ns, and the pulse width
t
WR, and PRECHARGE commands). CKE may be
IH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
overshoot for pin A12 is limited to V
t
CK = 7.5ns.
t
RFC (MIN) else CKE is LOW. The I
512Mb: x4, x8, x16 SDRAM
IL
undershoot: V
t
RP) begins 7.5ns/7ns after
©2000 Micron Technology, Inc. All rights reserved.
IL
(MIN) = –2V for
DD
Q + 1V for
Notes
DD
6