MT48LC64M8A2P-75:C Micron Technology Inc, MT48LC64M8A2P-75:C Datasheet - Page 47
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MT48LC64M8A2P-75:C
Manufacturer Part Number
MT48LC64M8A2P-75:C
Description
IC SDRAM 512MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC64M8A2TG-75C_TR.pdf
(68 pages)
Specifications of MT48LC64M8A2P-75:C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (64M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Organization
64Mx8
Density
512Mb
Address Bus
15b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
115mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC64M8A2P-75:C
Manufacturer:
MITSUBISHI
Quantity:
450
Notes
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
10.
11. AC timing and I
12. Other input signals are allowed to transition no more than once every two clocks and
13. I
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC functionality and are not dependent on any
18. The I
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
7. AC characteristics assume
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
9. Outputs measured at 1.5V with equivalent load:
biased at 1.4V.
with minimum cycle time and the outputs open.
operation over the full temperature range (0°C ≤ T
≤ 85°C for industrial) is ensured.
commands, before proper device operation is ensured. (V
ered up simultaneously. V
REFRESH command wake-ups should be repeated any time the
ment is exceeded.
sit between V
Q
t
a reference to V
High-Z.
crossover point. If the input transition time is longer than 1ns, then the timing is ref-
erenced at V
to Micron technical note TN-48-09.
are otherwise at valid V
cycle rate.
minimum cycle rate.
timing parameter.
frequency is altered for the test condition.
DD
HZ defines the time at which the output achieves the open circuit condition; it is not
DD
is dependent on output loading and cycle rates. Specified values are obtained
specifications are tested after the device is properly initialized.
DD
current will increase or decrease in a proportional amount by the amount the
t
CK = 7.5ns for -75 and -7E.
IL
IH
50pF
(MAX) and V
OH
DD
and V
or V
tests have V
IL
OL
IH
(or between V
. The last valid data element will meet
SS
or V
t
47
SS
T = 1ns.
IH
and V
t
t
t
.
DD
CKS; clock(s) specified as a reference only at minimum
WR plus
WR.
(MIN) and no longer at the 1.5V crossover point. Refer
IL
IL
, V
levels.
= 0V and V
SS
DD
Q must be at same potential.) The two AUTO
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Q = +3.3V; f = 1 MHz, T
IL
t
RP; clock(s) specified as a reference only at
and V
IH
IH
= 3V, with timing referenced to 1.5V
) in a monotonic manner.
A
512Mb: x4, x8, x16 SDRAM
≤ 70°C for commercial; –40°C ≤ T
DD
©2000 Micron Technology, Inc. All rights reserved.
A
and V
= 25°C; pin under test
t
OH before going
t
REF refresh require-
DD
Q must be pow-
Notes
A