AT45DB161D-SU Atmel, AT45DB161D-SU Datasheet - Page 19

• Manufacturer Part Number: AT45DB161D-SU
• Description: IC FLASH 16MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB161D-SU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 16M (4096 pages x 528 bytes)
• Speed: 66MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Architecture: Sectored
• Interface Type: SPI
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 128 KB x 16
• Current, Input, Leakage: 1 μA
• Current, Operating: 11 mA (Read), 12 mA (Program/Erase)
• Current, Output, Leakage: 1
• Data Retention: 20 yrs.
• Density: 16M
• Package Type: EIAJ SOIC
• Temperature, Operating: -40 to +85 °C
• Time, Access: 6 ns
• Time, Address Hold: 5
• Time, Address Setup: 5
• Time, Fall: 6.8 ns
• Time, Rise: 6.8 ns
• Voltage, Input, High: 1.89 to 2.52 V
• Voltage, Input, Low: 0.81 to 1.08 V
• Voltage, Output, High: 2.5 V
• Voltage, Output, Low: 0.4 V
• Voltage, Supply: 2.7 to 3.6 V
• Memory Configuration: 4096 Pages X 528 Bytes
• Clock Frequency: 66MHz
• Supply Voltage Range: 2.5V To 3.6V, 2.7V To 3.6V
• Rohs Compliant: Yes
• Access Time (max): 6ns
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3500N–DFLASH–05/10
10.2.2 Reading the Security Register
11.
11.1
11.2
The Security Register can be read by first asserting the CS pin and then clocking in an opcode of 77H followed by
three dummy bytes. After the last don't care bit has been clocked in, the content of the Security Register can be
clocked out on the SO pins. After the last byte of the Security Register has been read, additional pulses on the
SCK pin will simply result in undefined data being output on the SO pins.
Deasserting the CS pin will terminate the Read Security Register operation and put the SO pins into a high-
impedance state.
Figure 10-4. Read Security Register
Additional Commands
Main Memory Page to Buffer Transfer
A page of data can be transferred from the main memory to either buffer 1 or buffer 2. To start the operation for the
standard Atmel
be clocked into the device, followed by three address bytes comprised of two don’t care bits, 12 page address bits
(PA11 - PA0), which specify the page in main memory that is to be transferred, and 10 don’t care bits. To perform
a main memory page to buffer transfer for the binary page size (512-bytes), the opcode 53H for buffer 1 or 55H for
buffer 2, must be clocked into the device followed by three address bytes consisting of three don’t care bits, 12
page address bits (A20 - A9) which specify the page in the main memory that is to be transferred, and nine don’t
care bits. The CS pin must be low while toggling the SCK pin to load the opcode and the address bytes from the
input pin (SI). The transfer of the page of data from the main memory to the buffer will begin when the CS pin
transitions from a low to a high state. During the transfer of a page of data (t
the RDY/BUSY can be monitored to determine whether the transfer has been completed.
Main Memory Page to Buffer Compare
A page of data in main memory can be compared to the data in buffer 1 or buffer 2. To initiate the operation for
standard DataFlash page size, a 1-byte opcode, 60H for buffer 1 and 61H for buffer 2, must be clocked into the
device, followed by three address bytes consisting of two don’t care bits, 12 page address bits (PA11 - PA0) that
specify the page in the main memory that is to be compared to the buffer, and 10 don’t care bits. To start a main
memory page to buffer compare for a binary page size, the opcode 60H for buffer 1 or 61H for buffer 2, must be
clocked into the device followed by three address bytes consisting of three don’t care bits, 12 page address bits
(A20 - A9) that specify the page in the main memory that is to be compared to the buffer, and nine don’t care bits.
The CS pin must be low while toggling the SCK pin to load the opcode and the address bytes from the input pin
(SI). On the low-to-high transition of the CS pin, the data bytes in the selected main memory page will be compared
with the data bytes in buffer 1 or buffer 2. During this time (t
indicate that the part is busy. On completion of the compare operation, bit six of the status register is updated with
the result of the compare.
CS
SO
SI
Each transition
represents eight bits
®
DataFlash
Opcode
®
page size (528-bytes), a 1-byte opcode, 53H for buffer 1 and 55H for buffer 2, must
X
X
X
COMP
Data Byte
n
), the status register and the RDY/BUSY pin will
Data Byte
n + 1
XFR
Atmel AT45DB161D
), the status register can be read or
Data Byte
n + x
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