AT45DB161D-SU Atmel, AT45DB161D-SU Datasheet - Page 33

IC FLASH 16MBIT 66MHZ 8SOIC

AT45DB161D-SU

Manufacturer Part Number
AT45DB161D-SU
Description
IC FLASH 16MBIT 66MHZ 8SOIC
Manufacturer
Atmel

Specifications of AT45DB161D-SU

Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
16M (4096 pages x 528 bytes)
Speed
66MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Architecture
Sectored
Interface Type
SPI
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Current
15 mA
Mounting Style
SMD/SMT
Organization
128 KB x 16
Current, Input, Leakage
1 μA
Current, Operating
11 mA (Read), 12 mA (Program/Erase)
Current, Output, Leakage
1
Data Retention
20 yrs.
Density
16M
Package Type
EIAJ SOIC
Temperature, Operating
-40 to +85 °C
Time, Access
6 ns
Time, Address Hold
5
Time, Address Setup
5
Time, Fall
6.8 ns
Time, Rise
6.8 ns
Voltage, Input, High
1.89 to 2.52 V
Voltage, Input, Low
0.81 to 1.08 V
Voltage, Output, High
2.5 V
Voltage, Output, Low
0.4 V
Voltage, Supply
2.7 to 3.6 V
Memory Configuration
4096 Pages X 528 Bytes
Clock Frequency
66MHz
Supply Voltage Range
2.5V To 3.6V, 2.7V To 3.6V
Rohs Compliant
Yes
Access Time (max)
6ns
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Supply Current
15mA
Mounting
Surface Mount
Pin Count
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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3500N–DFLASH–05/10
21.2
21.3
21.4
21.5
Waveform 2 – SPI Mode 3 Compatible (for frequencies up to 66MHz)
Waveform 3 – Atmel RapidS Mode 0 (F
Waveform 4 – Atmel RapidS Mode 3 (F
Utilizing the Atmel RapidS Function
To take advantage of the Atmel
must be used to transmit data back and forth across the serial bus. The Atmel DataFlash
clock its data out on the falling edge of the SCK signal and clock data in on the rising edge of SCK.
For full clock cycle operation to be achieved, when the DataFlash is clocking data out on the falling edge of SCK,
the host controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host controller
should clock its data out on the rising edge of SCK in order to give the DataFlash a full clock cycle to latch the
incoming data in on the next rising edge of SCK.
SCK
SCK
SCK
SO
CS
CS
SO
CS
SO
SI
SI
SI
HIGH IMPEDANCE
HIGH Z
HIGH Z
t
CSS
t
CSS
t
SU
t
t
t
CSS
V
V
t
SU
t
SU
VALID IN
t
WL
t
WL
VALID IN
VALID IN
t
VALID OUT
WH
t
WH
t
VALID OUT
t
WH
V
t
HO
t
HO
t
®
H
t
H
RapidS
t
H
t
WL
VALID OUT
function's ability to operate at higher clock frequencies, a full clock cycle
t
HO
t
t
CSH
CSH
MAX
MAX
t
CSH
= 66MHz)
= 66MHz)
t
t
t
DIS
t
CS
HIGH IMPEDANCE
HIGH IMPEDANCE
DIS
t
CS
t
HIGH IMPEDANCE
DIS
CS
Atmel AT45DB161D
®
is designed to always
33

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