AT45DB161D-SU Atmel, AT45DB161D-SU Datasheet - Page 29
![IC FLASH 16MBIT 66MHZ 8SOIC](/photos/6/50/65032/453-8-soic_sml.jpg)
AT45DB161D-SU
Manufacturer Part Number
AT45DB161D-SU
Description
IC FLASH 16MBIT 66MHZ 8SOIC
Manufacturer
Atmel
Datasheets
1.AT45DB161D-CU.pdf
(51 pages)
2.AT45DB161D-SU.pdf
(6 pages)
3.AT45DB161D-SU.pdf
(53 pages)
Specifications of AT45DB161D-SU
Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
16M (4096 pages x 528 bytes)
Speed
66MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Architecture
Sectored
Interface Type
SPI
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Current
15 mA
Mounting Style
SMD/SMT
Organization
128 KB x 16
Current, Input, Leakage
1 μA
Current, Operating
11 mA (Read), 12 mA (Program/Erase)
Current, Output, Leakage
1
Data Retention
20 yrs.
Density
16M
Package Type
EIAJ SOIC
Temperature, Operating
-40 to +85 °C
Time, Access
6 ns
Time, Address Hold
5
Time, Address Setup
5
Time, Fall
6.8 ns
Time, Rise
6.8 ns
Voltage, Input, High
1.89 to 2.52 V
Voltage, Input, Low
0.81 to 1.08 V
Voltage, Output, High
2.5 V
Voltage, Output, Low
0.4 V
Voltage, Supply
2.7 to 3.6 V
Memory Configuration
4096 Pages X 528 Bytes
Clock Frequency
66MHz
Supply Voltage Range
2.5V To 3.6V, 2.7V To 3.6V
Rohs Compliant
Yes
Access Time (max)
6ns
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Supply Current
15mA
Mounting
Surface Mount
Pin Count
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT45DB161D-SU
Manufacturer:
ATMEL
Quantity:
106 020
Company:
Part Number:
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AYMEL
Quantity:
1
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Manufacturer:
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Quantity:
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Part Number:
AT45DB161D-SU-2.5
Manufacturer:
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20 000
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Manufacturer:
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Company:
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Manufacturer:
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3500N–DFLASH–05/10
16.
16.1
17.
Power-on/Reset State
When power is first applied to the device, or when recovering from a reset condition, the device will default to Mode
3. In addition, the output pin (SO) will be in a high impedance state, and a high-to-low transition on the CS pin will
be required to start a valid instruction. The mode (Mode 3 or Mode 0) will be automatically selected on every falling
edge of CS by sampling the inactive clock state.
Initial Power-up/Reset Timing Restrictions
At power up, the device must not be selected until the supply voltage reaches the V
t
above the Power-on Reset threshold value (V
respond to any commands. After power up is applied and the V
the t
Similarly, the t
device can perform a write (Program or Erase) operation. After initial power-up, the device will default in Standby
mode.
Table 16-1.
System Considerations
The Atmel
signals must rise and fall monotonically and be free from noise. Excessive noise or ringing on these pins can be
misinterpreted as multiple edges and cause improper operation of the device. The PC board traces must be kept to
a minimum distance or appropriately terminated to ensure proper operation. If necessary, decoupling capacitors
can be added on these pins to provide filtering against noise glitches.
As system complexity continues to increase, voltage regulation is becoming more important. A key element of any
voltage regulation scheme is its current sourcing capability. Like all Flash memories, the peak current for Atmel
DataFlash
requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current
starvation during programming or erase can lead to improper operation and possible data corruption.
VCSL
Symbol
t
t
V
VCSL
PUW
POR
VCSL
. During power-up, the internal Power-on Reset circuitry keeps the device in reset mode until the V
delay is required before the device can be selected in order to perform a read operation.
®
®
RapidS serial interface is controlled by the clock SCK, serial input SI and chip select CS pins. These
occur during the programming and erase operation. The regulator needs to supply this peak current
Parameter
V
Power-Up Device Delay before Write Allowed
Power-ON Reset Voltage
CC
PUW
Initial Power-up/Reset Timing Restrictions
(min.) to Chip Select low
delay is required after the V
POR
CC
rises above the Power-on Reset threshold value (V
). At this time, all operations are disabled and the device does not
CC
Min
1.5
70
is at the minimum operating voltage V
Typ
Atmel AT45DB161D
CC
Max
2.5
20
(min.) and further delay of
Units
ms
µs
V
POR
) before the
CC
CC
(min.),
rises
29