AT45DB161D-SU Atmel, AT45DB161D-SU Datasheet - Page 34

• Manufacturer Part Number: AT45DB161D-SU
• Description: IC FLASH 16MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB161D-SU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 16M (4096 pages x 528 bytes)
• Speed: 66MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Architecture: Sectored
• Interface Type: SPI
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 128 KB x 16
• Current, Input, Leakage: 1 μA
• Current, Operating: 11 mA (Read), 12 mA (Program/Erase)
• Current, Output, Leakage: 1
• Data Retention: 20 yrs.
• Density: 16M
• Package Type: EIAJ SOIC
• Temperature, Operating: -40 to +85 °C
• Time, Access: 6 ns
• Time, Address Hold: 5
• Time, Address Setup: 5
• Time, Fall: 6.8 ns
• Time, Rise: 6.8 ns
• Voltage, Input, High: 1.89 to 2.52 V
• Voltage, Input, Low: 0.81 to 1.08 V
• Voltage, Output, High: 2.5 V
• Voltage, Output, Low: 0.4 V
• Voltage, Supply: 2.7 to 3.6 V
• Memory Configuration: 4096 Pages X 528 Bytes
• Clock Frequency: 66MHz
• Supply Voltage Range: 2.5V To 3.6V, 2.7V To 3.6V
• Rohs Compliant: Yes
• Access Time (max): 6ns
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.6
34
Figure 21-1. Atmel RapidS Mode
Reset Timing
Note:
SO (OUTPUT)
Atmel AT45DB161D
MOSI = Master Out, Slave In
MISO = Master In, Slave Out
The Master is the host controller and the Slave is the Atmel DataFlash
The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK.
The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.
Slave
A.
B.
C.
D.
E.
F.
G. Master clocks in first bit of BYTE-SO
H. Slave clocks out second bit of BYTE-SO
I.
SI (INPUT)
MOSI
MISO
SCK
Master clocks out first bit of BYTE-MOSI on the rising edge of SCK
Slave clocks in first bit of BYTE-MOSI on the next rising edge of SCK
Master clocks out second bit of BYTE-MOSI on the same rising edge of SCK
Last bit of BYTE-MOSI is clocked out from the Master
Last bit of BYTE-MOSI is clocked into the slave
Slave clocks out first bit of BYTE-SO
Master clocks in last bit of BYTE-SO
RESET
CS
The CS signal should be in the high state before the RESET signal is deasserted
SCK
CS
A
1
B
MSB
HIGH IMPEDANCE
C
2
3
4
BYTE-MOSI
5
6
7
D
8
E
LSB
F
1
G
MSB
2
H
3
t RST
t REC
4
HIGH IMPEDANCE
BYTE-SO
5
6
t CSS
7
3500N–DFLASH–05/10
8
I
LSB
1