A3985SLDTR-T Allegro Microsystems Inc, A3985SLDTR-T Datasheet

IC MOSFET DRVR PROG DUAL 38TSSOP

A3985SLDTR-T

Manufacturer Part Number
A3985SLDTR-T
Description
IC MOSFET DRVR PROG DUAL 38TSSOP
Manufacturer
Allegro Microsystems Inc
Datasheet

Specifications of A3985SLDTR-T

Configuration
H Bridge
Input Type
Non-Inverting
Delay Time
120ns
Number Of Configurations
2
Number Of Outputs
8
Voltage - Supply
12 V ~ 50 V
Operating Temperature
-20°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
38-TSSOP
Device Type
Full Bridge
Module Configuration
Full Bridge
Peak Output Current
500nA
Output Resistance
19ohm
Input Delay
120ns
Output Delay
120ns
Supply Voltage Range
12V To 50V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Peak
-
High Side Voltage - Max (bootstrap)
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
620-1180-2
Features and Benefits
▪ Serial interface for full digital control
▪ Dual full-bridge gate drive for N-channel MOSFETs
▪ Dual 6-bit DAC current reference
▪ Operation over 12 to 50 V supply voltage range
▪ Synchronous rectification
▪ Cross-conduction protection
▪ Adjustable mixed decay
▪ Fixed off-time PWM current control
▪ Low-current idle mode
Package: 38 pin TSSOP (suffix LD)
3985-DS, Rev. 4
Approximate size
Typical Application
Dual Full-Bridge MOSFET Driver
Description
The A3985 is a flexible dual full-bridge gate driver suitable
for driving a wide range of higher power industrial bipolar 2-
phase stepper motors or 2-phase brushless dc motors. It can
also be used to drive two individual torque motors or solenoid
actuators. Motor power is provided by external N-channel power
MOSFETs at supply voltages from 12 to 50 V.
Full digital control is provided by two serially-accessible
registers that allow programming of off-time, blank-time,
dead-time, mixed decay ratios, synchronous rectification,
master clock source selection, and division ratio and idle
mode. All internal timings are derived from a master clock
that can be generated on-chip or provided by an external
clock such as the system clock of the master controller. A
programmable divider allows for a wide range of external
system clock frequencies.
The internal fixed off-time PWM current-control timing is
programmed via the serial interface to operate in slow, fast,
and mixed current-decay modes. The desired load-current level
and direction is set via the serial port with a direction bit and
two 6-bit linear DACs in conjunction with a reference voltage.
The seven bits of control allow maximum flexibility in torque
Continued on the next page…
Digitally Programmable
A3985

A3985SLDTR-T Summary of contents

Page 1

Features and Benefits ▪ Serial interface for full digital control ▪ Dual full-bridge gate drive for N-channel MOSFETs ▪ Dual 6-bit DAC current reference ▪ Operation over supply voltage range ▪ Synchronous rectification ▪ Cross-conduction protection ...

Page 2

... MOSFETs is provided by a bootstrap capacitor. Efficiency is enhanced by using synchronous rectification and the power FETs are protected from shoot-through by integrated crossover-control Selection Guide Part Number A3985SLDTR-T Tape and reel, 4000 pieces per reel Absolute Maximum Ratings Characteristic Supply Voltage Logic Supply Voltage ...

Page 3

A3985 +5 V VDD Bandgap V REF REF SDO SDI STR Serial Port SCK WC ENABLE V REF OSC Programmable Divider Oscillator Dual Full-Bridge MOSFET Driver Functional Block Diagram VBB Regulator Phase 1A High-Side Drive V REG 6-bit Low-Side DAC ...

Page 4

A3985 ELECTRICAL CHARACTERISTICS at T Characteristics Supply and Reference Load Supply Voltage Range Load Supply Current Load Supply Idle Current Logic Supply Voltage Range Logic Supply Current Logic Supply Idle Current Regulator Output Bootstrap Diode Forward Voltage Gate Output Drive ...

Page 5

A3985 ELECTRICAL CHARACTERISTICS, continued Characteristics Current Control Blank Time Fixed Off-Time Reference Input Voltage Internal Reference Voltage Current Trip Point Error 2 Reference Input Current 1 Internal Oscillator Frequency Maximum Clock Input Frequency Master Clock Frequency Protection VREG ...

Page 6

A3985 ELECTRICAL CHARACTERISTICS, continued Characteristics Serial Data Timing Serial Clock High Time Serial Clock Low Time Strobe Lead Time Strobe Lag Time Strobe High Time Data Out Enable Time Data Out Disable Time Data Out Valid Time from ...

Page 7

A3985 Basic Operation The A3985 is a highly-configurable dual full-bridge FET driver with built-in digital current control. All features are accessed through a simple SPI (Serial Peripheral Interface) compatible serial port, allowing multiple motors to be con- trolled with as ...

Page 8

A3985 SDI, SCK, STR, SDO These are the serial port interface pins. Data is clocked into SDI by a clock signal on SCK. The data is then latched by a signal on STR. Note, however, that SCK must be high ...

Page 9

A3985 through the motor winding and the current sense resistor, RSENSEx. When the voltage across RSENSEx equals the DAC output voltage, the current sense comparator resets the PWM latch, which turns off the source MOSFET (slow decay mode) or the ...

Page 10

A3985 gramming the Fast Decay Time bits in the Control register (Word1, Bits D8 through D11 the device effectively operates in full fast decay mode. Selecting between slow decay and mixed decay is done by programming the Mode ...

Page 11

A3985 to 0 disables Bridge 1, with all drivers off (see Internal PWM Current Control, in the Functional Description section). D7 – Bridge 1 Phase Controls the direction of output cur- rent for Bridge (load S1A 0 L ...

Page 12

A3985 Note that, for t > the device effectively operates in FD OFF full fast-decay mode. D12 and D13 – Master Clock Control An internal oscillator can be used for the timing functions, and if more precise control ...

Page 13

A3985 Current Sensing To minimize inaccuracies in sensing the I level caused by ground-trace IR drops, the sense resistor, RSENSEx, should have an independent return to the supply ground star point. For low-value sense resistors, the IR drops in the ...

Page 14

A3985 Pin-out Diagram Terminal List Table Number ...

Page 15

A3985 9.70 ±0. 38X 0.10 C 0.22 ±0.05 0.50 Copyright ©2005-2008, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right ...

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