ISL88550AIRZ Intersil, ISL88550AIRZ Datasheet - Page 16

• Manufacturer Part Number: ISL88550AIRZ
• Description: IC PWM CONTROLLER 28TQFN
• Manufacturer: Intersil

Specifications of ISL88550AIRZ

• Applications: PWM Controller
• Voltage - Input: 2 ~ 25 V
• Current - Supply: 25µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TQFN
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

nominal regulation voltage, the ISL88550A pulls POK1 low.
Any fault condition forces POK1 low until the fault latch is
cleared by toggling SHDNA# or cycling AV
1V. For logic level output voltages, connect an external
pull-up resistor between POK1 and AV
works well in most applications. Note that the POK1 window
detector is completely independent of the overvoltage and
undervoltage protection fault detectors and the state of
VTTS and VTTR.
SHDNA# and Output Discharge
The SHDNA# input corresponds to the Buck Regulator and
places the Buck Regulator’s portion of the IC in a low power
mode (see “Electrical Specifications” table on page 3).
SHDNA# is also used to reset a fault signal such as an
overvoltage or undervoltage fault.
When output discharge is enabled (OVP/UVP = AV
open) and SHDNA# is pulled low, or if UVP is enabled
(OVP/UVP = AV
set point, the ISL88550A discharges the Buck Regulator
output (via the OUT input) through an internal 15
ground. While the output is discharging, the PWM controller
is disabled, but the reference remains active to provide an
accurate threshold.
When output discharge is disabled (OVP/UVP = REF or
GND), the controller does not actively discharge the Buck
Output. Under these conditions, the Buck Output discharge
rate is determined by the load current and its output
capacitance. The Buck Regulator detects and latches the
discharge mode state set by OVP/UVP setting on start-up.
STBY#
The STBY# input is an active low input that is used to
shutdown only the VTT output. When STBY# is low, VTT is
high impedance, but the VTTR output is still active if
SHDNA# is high. VTT and VTTR are pulled to 0V when
SHDNA is low.
Power OK (POK2)
POK2 is the open-drain output for a window comparator that
continuously monitors the VTTS input and VTTR output.
POK2 is high impedance as long as the output voltage is
within ±10% of the nominal regulation voltage as set by
REFIN. When V
SHDNA#
AV DD
AV
GND
TABLE 2. SHUTDOWN AND STANDBY CONTROL LOGIC
DD
STBY#
AV
GND
X
DD
VTTS
DD
) and V
or V
OUTPUT
BUCK
OFF
ON
ON
VTTR
OUT
16
falls to 70% of its regulation
rise 10% above or 10%
(Discharge to
Impedance)
OFF
(High
OFF
VTT
0V)
ON
DD
. A 100kΩ resistor
DD
power below
(Tracking ½
Ω
REFIN)
VTTR
switch to
OFF
DD
ON
ON
or
ISL88550A
below their nominal regulation voltage, the ISL88550A pulls
POK2 low. For logic level output voltages, connect an
external pull-up resistor between POK2 and AV
resistor works well in most applications. Note that the POK2
window detector is completely independent of the
overvoltage and undervoltage protection fault detectors and
the state of VDDQ.
Current Limit (LDO for VTT and VTTR Buffer)
The VTT output is a linear regulator that regulates the input
(VTTI) to ½ the V
is at the VTTS input (see Figure 21). VTT is capable of
sourcing up to 2.5A and sinking up to -2.0A continuously.
The current limit for VTT and VTTR is typically +3.0A/-2.5A
and ±40mA respectively. When the current limit for either
output is reached, the outputs regulate the current not the
voltage. The current limits for both VTT and VTTR can be
reduced from their full values by forcing the voltage at the SS
pin below 1.6V (typical), or by tying a resistor (R
the SS pin and ground such that 4µA*R
POK2 is pulled low when REFIN is <0.8V.
Fault Protection
The ISL88550A provides overvoltage/undervoltage fault
protection in the buck controller. Select OVP/UVP to enable
and disable fault protection as shown in Table 3. Once
activated, the controller continuously monitors the output for
undervoltage and overvoltage fault conditions. Any VDDQ
shutdown due to OVP, UVP, OTP or SHDNA# = 0 should
also discharge VTT to 0V.
Overvoltage Protection (OVP)
When the output voltage rises above 114% of the nominal
regulation voltage and OVP is enabled (OVP/UVP = AVDD
or open), the OVP circuit sets the fault latch, shuts down the
PWM controller and immediately pulls UGATE low and
forces LGATE high. This turns on the synchronous rectifier
MOSFET with 100% duty cycle, rapidly discharging the
output capacitor and clamping the output to ground. Note
that immediately latching LGATE high can cause the output
voltage to go slightly negative due to energy stored in the
output LC circuit at the instant the OVP occurs. If the load
cannot tolerate a negative voltage, place a power Schottky
diode across the output to act as a reverse polarity clamp.
Toggle SHDNA# or cycle AVDD power below 1V to clear the
fault latch and restart the controller. OVP is disabled when
OVP/UVP is connected to REF or GND (see Table 3). OVP
only applies to the Buck Output. The VTT and VTTR Outputs
do not have overvoltage protection. When VDDQ is
discharged to 0V due to OVP, VTT is also discharged to 0V.
REFIN
voltage. The feedback point for VTT
SS
is less than 1.6V.
DD
SS
. A 100kΩ
) between
April 23, 2008
FN6168.3