TMP86C909XB Toshiba, TMP86C909XB Datasheet - Page 153
TMP86C909XB
Manufacturer Part Number
TMP86C909XB
Description
EMULATION CHIP FOR TMP86F SDIP
Manufacturer
Toshiba
Datasheet
1.TMP86C909XB.pdf
(201 pages)
Specifications of TMP86C909XB
Accessory Type
Adapter
For Use With/related Products
TMP86F SDIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 153 of 201
- Download datasheet (2Mb)
14.4 Access to the Flash Memory Area
Example :After chip erasure, the program in the RAM area writes data 3FH to address F000H.
; #### Flash Memory Chip erase Process ####
sLOOP1:
; #### Flash Memory Write Process ####
sLOOP2:
sLOOP3:
DI
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
CMP
JR
LD
LD
LD
LD
LD
CMP
JR
LD
JP
(FLSCR),0011_1000B
IX,0F555H
IY,0FAAAH
HL,0F000H
(IX),0AAH
(IY),55H
(IX),80H
(IX),0AAH
(IY),55H
(IX),10H
W,(IX)
W,(IX)
NZ,sLOOP1
(IX),0AAH
(IY),55H
(IX),0A0H
(HL),3FH
W,(HL)
W,(HL)
NZ,sLOOP2
(FLSCR),1100_1000B
sLOOP3
Page 142
: Disable interrupts (IMF←"0")
: Enable command sequence execution.
: 1st bus write cycle
: 2nd bus write cycle
: 3rd bus write cycle
: 4th bus write cycle
: 5th bus write cycle
: 6th bus write cycle
: Loop until the same value is read.
: 1st bus write cycle
: 2nd bus write cycle
: 3rd bus write cycle
: 4th bus write cycle, (F000H)=3FH
: Loop until the same value is read.
: Disable command sequence execution.
TMP86F409NG
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