TMP86C993XB Toshiba, TMP86C993XB Datasheet - Page 36

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TMP86C993XB

Manufacturer Part Number
TMP86C993XB
Description
EMULATION CHIP FOR TMP86F SSOP
Manufacturer
Toshiba
Datasheet

Specifications of TMP86C993XB

Accessory Type
Adapter
For Use With/related Products
TMP86F SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
2.2
System Clock Controller
(1)
(2)
enable flag (EF). After the interrupt is generated, the program operation is resumed from the instruction
following the IDLE1/2 and SLEEP1/2 modes start instruction. Normally, the interrupt latches (IL) of
the interrupt source used for releasing must be cleared to “0” by load instructions.
interrupt enable flag (EF) and the interrupt processing is started. After the interrupt is processed, the
program operation is resumed from the instruction following the instruction, which starts IDLE1/2 and
SLEEP1/2 modes.
・ Start the IDLE1/2 and SLEEP1/2 modes
・ Release the IDLE1/2 and SLEEP1/2 modes
IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled by the individual interrupt
IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled with the individual
Note:When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2
Normal release mode (IMF = “0”)
Interrupt release mode (IMF = “1”)
and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2<IDLE> to “1”.
These modes are selected by interrupt master enable flag (IMF). After releasing IDLE1/2 and
SLEEP1/2 modes, the SYSCR2<IDLE> is automatically cleared to “0” and the operation mode
is returned to the mode preceding IDLE1/2 and SLEEP1/2 modes.
After releasing reset, the operation mode is started from NORMAL1 mode.
modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2
modes will not be started.
After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2
IDLE1/2 and SLEEP1/2 modes include a normal release mode and an interrupt release mode.
IDLE1/2 and SLEEP1/2 modes can also be released by inputting low level on the RESET pin.
Page 22
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