TMP86C993XB Toshiba, TMP86C993XB Datasheet - Page 89
TMP86C993XB
Manufacturer Part Number
TMP86C993XB
Description
EMULATION CHIP FOR TMP86F SSOP
Manufacturer
Toshiba
Datasheet
1.TMP86C993XB.pdf
(246 pages)
Specifications of TMP86C993XB
Accessory Type
Adapter
For Use With/related Products
TMP86F SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8.3.4
be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the SFR area,
address trap reset will be generated.
fc [s] (1.5 μs @ fc = 16.0 MHz).
Address Trap Reset
While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an attempt
When an address trap reset request is generated, the internal hardware is reset. The reset time is maximum 24/
Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-
frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have
inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an
approximate value because it has slight errors.
Page 75
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