TMP86C993XB Toshiba, TMP86C993XB Datasheet - Page 52

• Manufacturer Part Number: TMP86C993XB
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba

Specifications of TMP86C993XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3
Interrupt Sequence
3.3
Interrupt Enable Registers
3.3.1
(003BH, 003AH)
EIRH,EIRL
“0” by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 μs @16 MHz) after the
completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return
instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing
chart of interrupt acceptance processing.
(0032H)
EIRE
An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to
Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to
Note 3: Do not clear IL with read-modify-write instructions such as bit operations.
Note 1: *: Don’t care
Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to “1” at the same time.
Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to
Interrupt Sequence
Interrupt acceptance processing is packaged as follows.
Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved.
"0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable
interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on
interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be
executed before setting IMF="1".
"0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable
interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on
interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be
executed before setting IMF="1".
a. The interrupt master enable flag (IMF) is cleared to “0” in order to disable the acceptance of any
b. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.
c. The contents of the program counter (PC) and the program status word, including the interrupt master
d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector
e. The instruction stored at the entry address of the interrupt service program is executed.
EF15
15
following interrupt.
enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile,
the stack pointer (SP) is decremented by 3.
table, is transferred to the program counter.
EF21 to EF4
EF14
14
IMF
EF13
13
EIRH (003BH)
EF12
12
Individual-interrupt enable flag
(Specified for each bit)
Interrupt master enable flag
EF11
11
EF10
10
Page 38
EF9
9
EF8
8
0:
1:
0:
1:
Disables the acceptance of each maskable interrupt.
Enables the acceptance of each maskable interrupt.
Disables the acceptance of all maskable interrupts
Enables the acceptance of all maskable interrupts
EF7
7
7
−
EF6
6
6
−
EF21
EF5
5
5
EIRL (003AH)
EIRE (0032H)
EF20
EF4
4
4
(Initial value: 00000000 0000***0)
EF19
3
3
TMP86FH92DMG
(Initial value: **000000)
EF18
2
2
EF17
1
1
EF16
IMF
R/W
0
0