C8051T600QDB Silicon Laboratories Inc, C8051T600QDB Datasheet - Page 140
C8051T600QDB
Manufacturer Part Number
C8051T600QDB
Description
BOARD SOCKET DAUGHTER QFN
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051T600EDB.pdf
(188 pages)
Specifications of C8051T600QDB
Module/board Type
Socket Module - QFN
Data Bus Width
8 bit
Operating Supply Voltage
+ 1.8 V to + 3.6 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051T600DK
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1406
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C8051T600/1/2/3/4/5/6
24.2.2. 9-Bit UART
The 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a program-
mable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in
TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P
in register PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data
bit goes into RB80 (SCON0.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not met,
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur if
enabled when either TI0 or RI0 is set to 1.
MARK
START
STOP
D0
D1
D2
D3
D4
D5
D6
D7
D8
BIT
BIT
SPACE
BIT TIMES
BIT SAMPLING
Figure 24.5. 9-Bit UART Timing Diagram
140
Rev. 1.2
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