Z8FMC160100KIT Zilog, Z8FMC160100KIT Datasheet - Page 118
![KIT DEV FOR Z8 ENCORE Z8FMC16100](/photos/9/6/90634/z8fmc160100kit_sml.jpg)
Z8FMC160100KIT
Manufacturer Part Number
Z8FMC160100KIT
Description
KIT DEV FOR Z8 ENCORE Z8FMC16100
Manufacturer
Zilog
Series
Z8 Encore! MC™r
Datasheets
1.Z8FMC160100KIT.pdf
(7 pages)
2.Z8FMC160100KIT.pdf
(383 pages)
3.Z8FMC160100KIT.pdf
(20 pages)
Specifications of Z8FMC160100KIT
Main Purpose
Power Management, Motor Control
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
Z8FMC16100
Primary Attributes
3-Ph DC Motors
Secondary Attributes
Graphic User Interface
Processor To Be Evaluated
Z8FMC16100
Data Bus Width
8 bit
Interface Type
USB
For Use With
269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3639
- Current page: 118 of 383
- Download datasheet (5Mb)
PS024613-0910
Bit Position
[6]
TPOL
Value (H)
Description
Timer Input/Output Polarity
This bit is a function of the current operating mode of the timer. It
determines the polarity of the input and/or output signal. When the timer is
disabled, the Timer Output signal is set to the value of this bit.
ONE-SHOT mode—If the timer is enabled the Timer Output signal
pulses (changes state) for one system clock cycle after timer Reload.
CONTINUOUS mode—If the timer is enabled the Timer Output signal is
complemented after timer Reload.
COUNTER mode—If the timer is enabled the Timer Output signal is
complemented after timer reload.
0 = Count occurs on the rising edge of the Timer Input signal.
1 = Count occurs on the falling edge of the Timer Input signal.
PWM SINGLE OUTPUT mode—When enabled, the Timer Output is
forced to TPOL after PWM count match and forced back to TPOL after
Reload.
CAPTURE mode—If the timer is enabled, the Timer Output signal is
complemented after timer Reload.
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
COMPARE mode—The Timer Output signal is complemented after
timer Reload.
GATED mode—The Timer Output signal is complemented after timer
Reload.
0 = Timer counts when the Timer Input signal is High and interrupts are
generated on the falling edge of the Timer Input.
1 = Timer counts when the Timer Input signal is Low and interrupts are
generated on the rising edge of the Timer Input.
CAPTURE/COMPARE mode—If the timer is enabled, the Timer Output
signal is complemented after timer Reload
0 = Counting starts on the first rising edge of the Timer Input signal. The
current count is captured on subsequent rising edges of the Timer Input
signal.
1 = Counting starts on the first falling edge of the Timer Input signal. The
current count is captured on subsequent falling edges of the Timer Input
signal.
Z8FMC16100 Series Flash MCU
Product Specification
Timer 0 Control Registers
106
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