Z8FMC160100KIT Zilog, Z8FMC160100KIT Datasheet - Page 274
![KIT DEV FOR Z8 ENCORE Z8FMC16100](/photos/9/6/90634/z8fmc160100kit_sml.jpg)
Z8FMC160100KIT
Manufacturer Part Number
Z8FMC160100KIT
Description
KIT DEV FOR Z8 ENCORE Z8FMC16100
Manufacturer
Zilog
Series
Z8 Encore! MC™r
Datasheets
1.Z8FMC160100KIT.pdf
(7 pages)
2.Z8FMC160100KIT.pdf
(383 pages)
3.Z8FMC160100KIT.pdf
(20 pages)
Specifications of Z8FMC160100KIT
Main Purpose
Power Management, Motor Control
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
Z8FMC16100
Primary Attributes
3-Ph DC Motors
Secondary Attributes
Graphic User Interface
Processor To Be Evaluated
Z8FMC16100
Data Bus Width
8 bit
Interface Type
USB
For Use With
269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3639
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Table 139. AC Characteristics
Table 140. POR and VBO Electrical Characteristics and Timing
PS024613-0910
Symbol
F
F
T
T
T
Symbol
V
V
T
T
SYSCLK
XTAL
XIN
XINH
XINL
ANA
POR
POR
VBO
On-Chip Peripheral AC and DC Electrical Characteristics
Parameter
System clock frequency
Crystal oscillator frequency
System clock period
System clock high time
System clock low time
Parameter
Power-On Reset
voltage threshold
Voltage Brownout reset
voltage threshold
V
Starting V
ensure valid Power-On
Reset
Power-On Reset
analog delay
Power-On Reset digital
delay
POR
Table 140
circuits.
–V
VBO
DD
voltage to
provides electrical characteristics and timing information for the POR and VBO
Minimum
2.20
2.15
—
—
—
T
A
T
Minimum Maximum
0.032768
= –40 ºC to 105 ºC
A
V
= –40 ºC to 105 ºC
50
20
20
—
DD
Typical
2.45
2.40
V
5.0
= 2.7–3.6 V
50
50
SS
On-Chip Peripheral AC and DC Electrical Characteristics
1
20.0
20.0
30
30
—
Maximum
2.70
2.65
100
—
—
—
Z8FMC16100 Series Flash MCU
Units Conditions
MHz
MHz System clock frequencies
ns
ns
ns
Units Conditions
mV
ms
ms
V
V
V
below the crystal oscillator
minimum require an external
clock driver.
T
T
T
CLK
CLK
CLK
Product Specification
V
V
V
Digital Reset delay
follows T
50 WDT Oscillator
cycles (10 kHz) + 16
System Clock cycles
(20 MHz).
= 1 ÷ F
= 50 ns.
= 50 ns.
DD
DD
DD
= V
= V
> V
POR
VBO
POR
SYSCLK
ANA
.
.
; T
.
POR
.
262
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