Z8FMC160100KIT Zilog, Z8FMC160100KIT Datasheet - Page 173
![KIT DEV FOR Z8 ENCORE Z8FMC16100](/photos/9/6/90634/z8fmc160100kit_sml.jpg)
Z8FMC160100KIT
Manufacturer Part Number
Z8FMC160100KIT
Description
KIT DEV FOR Z8 ENCORE Z8FMC16100
Manufacturer
Zilog
Series
Z8 Encore! MC™r
Datasheets
1.Z8FMC160100KIT.pdf
(7 pages)
2.Z8FMC160100KIT.pdf
(383 pages)
3.Z8FMC160100KIT.pdf
(20 pages)
Specifications of Z8FMC160100KIT
Main Purpose
Power Management, Motor Control
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
Z8FMC16100
Primary Attributes
3-Ph DC Motors
Secondary Attributes
Graphic User Interface
Processor To Be Evaluated
Z8FMC16100
Data Bus Width
8 bit
Interface Type
USB
For Use With
269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3639
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I
PS024613-0910
2
C Master/Slave Controller
Architecture
The I
devices are bus-compatible with the I
signal (SDA) and a serial clock signal (SCL) bidirectional lines. The features of I
controller include:
•
•
•
•
•
•
•
•
•
Figure 27
Operates in MASTER/SLAVE or SLAVE ONLY modes.
Supports arbitration in a multimaster environment (MASTER/SLAVE mode).
Supports data rates up to 400 Kbps.
7-bit or 10-bit slave address recognition (interrupt only on address match).
Optional general call address recognition.
Optional digital filter on receive SDA, SCL lines.
Optional interactive receive mode allows software interpretation of each received
address and/or data byte before acknowledging.
Unrestricted number of data bytes per transfer.
Baud Rate Generator can be used as a general-purpose timer with an interrupt if the I
controller is disabled.
2
C Master/Slave Controller ensures that the Z8FMC16100 Series Flash MCU
displays the architecture of the I
2
C protocol. The I
2
C controller.
Z8FMC16100 Series Flash MCU
2
C bus consists of the serial data
Product Specification
Architecture
2
2
C
C
161
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