Z8FMC160100KIT Zilog, Z8FMC160100KIT Datasheet - Page 164
![KIT DEV FOR Z8 ENCORE Z8FMC16100](/photos/9/6/90634/z8fmc160100kit_sml.jpg)
Z8FMC160100KIT
Manufacturer Part Number
Z8FMC160100KIT
Description
KIT DEV FOR Z8 ENCORE Z8FMC16100
Manufacturer
Zilog
Series
Z8 Encore! MC™r
Datasheets
1.Z8FMC160100KIT.pdf
(7 pages)
2.Z8FMC160100KIT.pdf
(383 pages)
3.Z8FMC160100KIT.pdf
(20 pages)
Specifications of Z8FMC160100KIT
Main Purpose
Power Management, Motor Control
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
Z8FMC16100
Primary Attributes
3-Ph DC Motors
Secondary Attributes
Graphic User Interface
Processor To Be Evaluated
Z8FMC16100
Data Bus Width
8 bit
Interface Type
USB
For Use With
269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3639
- Current page: 164 of 383
- Download datasheet (5Mb)
PS024613-0910
Multimaster Operation
Transfer Format Phase Equals One
Figure 26
forms are depicted for SCK, one for CLKPOL reset to 0, and another for CLKPOL set to 1.
In a multimaster SPI system, all SCK pins are tied together, all MOSI pins are tied together,
and all MISO pins are tied together. All SPI pins must then be configured in OPEN-DRAIN
mode to prevent bus contention. At any time, only one SPI device is configured as the mas-
ter and all other SPI devices on the bus are configured as slaves. The master enables a sin-
gle slave by asserting the SS pin on that slave only. Then, the single master drives data out
its SCK and MOSI pins to the SCK and MOSI pins on the slaves (including those which are
not enabled). The enabled slave drives data out its MISO pin to the MISO master pin.
For a master device operating in a multimaster system, if the SS pin is configured as an
input and is driven Low by another master, the COL bit is set to 1 in the SPI Status register.
The COL bit indicates the occurrence of a multimaster collision (mode fault error
condition).
Input Sample Time
(CLKPOL = 0)
(CLKPOL = 1)
displays the timing diagram for an SPI transfer in which
MOSI
MISO
SCK
SCK
SS
Figure 26. SPI Timing When Phase is 1
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Z8FMC16100 Series Flash MCU
Bit 3
Bit 3
Product Specification
Bit 2
Bit 2
PHASE
Multimaster Operation
Bit 1
Bit 1
is 1. Two wave-
Bit 0
Bit 0
152
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