Z8FMC160100KIT Zilog, Z8FMC160100KIT Datasheet - Page 142
![KIT DEV FOR Z8 ENCORE Z8FMC16100](/photos/9/6/90634/z8fmc160100kit_sml.jpg)
Z8FMC160100KIT
Manufacturer Part Number
Z8FMC160100KIT
Description
KIT DEV FOR Z8 ENCORE Z8FMC16100
Manufacturer
Zilog
Series
Z8 Encore! MC™r
Datasheets
1.Z8FMC160100KIT.pdf
(7 pages)
2.Z8FMC160100KIT.pdf
(383 pages)
3.Z8FMC160100KIT.pdf
(20 pages)
Specifications of Z8FMC160100KIT
Main Purpose
Power Management, Motor Control
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
Z8FMC16100
Primary Attributes
3-Ph DC Motors
Secondary Attributes
Graphic User Interface
Processor To Be Evaluated
Z8FMC16100
Data Bus Width
8 bit
Interface Type
USB
For Use With
269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3639
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- Download datasheet (5Mb)
Table 69. LIN-UART Status 0 Register - LIN mode (U0STAT0)
PS024613-0910
BITS
FIELD
RESET
R/W
ADDR
RDA
R
7
0
Receive Data Available (RDA)—
received data. Reading the Receive Data register clears this bit.
Physical Layer Error (PLE)—
match when a LIN slave or master is transmitting. This could be caused by a fault in the
physical layer or multiple devices driving the bus simultaneously. Reading the Status 0
register or the Receive Data register clears this bit.
Receive Data and Autobaud Overrun Error (OE)—
UART operation if a receive data overrun error occurs. This bit is also set during LIN
Slave autobaud if the BRG counter overflows before the end of the autobaud sequence,
indicating the receive activity was not an autobaud character or the master baud rate is too
slow. The ATB status bit will also be set in this case. This bit is cleared by reading the
Receive Data register.
Framing Error (FE)—
reception) was detected. Reading the Receive Data register clears this bit.
Break Detect (BRKD)—
at least 4 bit times occurred (Wake-up event) or (b) in Slave Wait Break state and a break
of at least 11 bit times occurred (Break event) or (c) in Slave Active state and a break of at
least 10 bit times occurs. Reading the Status 0 register or the Receive Data register clears
this bit.
Transmitter Data Register Empty (TDRE)—
register is empty and ready for additional data. Writing to the Transmit Data register resets
this bit.
Transmitter Empty (TXE)—
character transmission is finished.
LIN Slave Autobaud Complete (ATB)—
autobaud character is received. If the ABIEN bit is set in the LIN Control register, then a
receive interrupt is generated when this bit is set. Reading the Status 0 register clears this
bit. This bit will be 0 in LIN MASTER mode.
PLE
R
6
0
ABOE
This bit indicates that a framing error (no STOP bit following data
R
5
0
This bit is set in LIN mode if (a) in LinSleep state and a break of
This bit indicates that the transmit shift register is empty and
This bit indicates that transmit and receive data do not
This bit indicates that the Receive Data register has
FE
R
4
0
F41H
This bit is set in LIN SLAVE mode when an
BRKD
This bit indicates that the Transmit Data
R
3
0
Z8FMC16100 Series Flash MCU
This bit is set just as in normal
TDRE
R
2
1
Product Specification
LIN-UART Status 0 Register
TXE
R
1
1
ATB
R
0
0
130
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