Z8FMC160100KIT Zilog, Z8FMC160100KIT Datasheet - Page 191
![KIT DEV FOR Z8 ENCORE Z8FMC16100](/photos/9/6/90634/z8fmc160100kit_sml.jpg)
Z8FMC160100KIT
Manufacturer Part Number
Z8FMC160100KIT
Description
KIT DEV FOR Z8 ENCORE Z8FMC16100
Manufacturer
Zilog
Series
Z8 Encore! MC™r
Datasheets
1.Z8FMC160100KIT.pdf
(7 pages)
2.Z8FMC160100KIT.pdf
(383 pages)
3.Z8FMC160100KIT.pdf
(20 pages)
Specifications of Z8FMC160100KIT
Main Purpose
Power Management, Motor Control
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
Z8FMC16100
Primary Attributes
3-Ph DC Motors
Secondary Attributes
Graphic User Interface
Processor To Be Evaluated
Z8FMC16100
Data Bus Width
8 bit
Interface Type
USB
For Use With
269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3639
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- Download datasheet (5Mb)
PS024613-0910
S
Figure 34. Data Transfer Format—Slave Transmit Transaction with 7-bit Address
Slave Address
6. The I
7. The software responds by reading the I2CISTAT register, finding the
8. The master and slave loops through steps 5 to 7 until the master detects a Not
9. The master sends the
Slave Transmit Transaction with 7-bit Address
The data transfer format for a master reading data from a slave in 7-bit address mode is
shown in Figure 37. The procedure that follows describes the I
operating as a slave in 7-bit addressing mode and transmitting data to the bus master.
1. The software configures the controller for operation as a slave in 7-bit addressing
2. The master initiates a transfer, sending the address byte. The SLAVE mode I
3. The software responds to the interrupt by reading the I2CISTAT register, thereby
Acknowledge, depending on the state of the
controller generates the receive data interrupt by setting the
register.
then reading the I2CDATA register, which clears the
accept only one more data byte, it sets the
Acknowledge instruction or runs out of data to send.
cause the I
I2CISTAT register). Because the slave received data from the master, the software
takes no action in response to the STOP interrupt other than reading the I2CISTAT
register to clear the
mode, as follows:
(a) Initialize the
(b) Optionally set the
(c) Initialize the
(d) Set
controller finds an address match and detects that the R/W bit = 1 (read by the master
from the slave). The I
the transaction. The
The
clearing the
byte into the I2CDATA register. The software sets the
or MASTER/SLAVE mode with 7-bit addressing.
RD
2
C controller receives the first byte and responds with Acknowledge or Not
IEN
bit is set to 1, indicating a Read from the slave.
2
C controller to assert the STOP interrupt (the
SAM
= 1 in the I
bit. Because
MODE
SLA[6:0]
R = 1
STOP
SAM
STOP
2
GCE
C controller acknowledges, indicating that it is ready to accept
field in the I
2
C Control register. Set
bit in the I2CISTAT register is set to 1, causing an interrupt.
bit.
bit.
or
bits in the I
RD
RESTART
A
= 1, the software responds by loading the first data
2
C Mode register for either SLAVE ONLY mode
Data
2
signal on the bus. Either of these signals can
C Slave Address register.
NAK
NAK
bit in the I2CCTL register.
NAK
Z8FMC16100 Series Flash MCU
bit in the I2CCTL register. The I
A
= 0 in the I
RDRF
TXI
STOP
Data
2
bit. If the software can
bit in the I2CCTL register
RDRF
C Master/Slave Controller
Product Specification
2
bit = 1 in the
C Control register.
bit in the I2CISTAT
RDRF
Slave Transactions
A
bit = 1, and
2
P/S
C
2
C
179
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