DK86065-2 Fujitsu Semiconductor America Inc, DK86065-2 Datasheet - Page 2
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DK86065-2
Manufacturer Part Number
DK86065-2
Description
KIT EVAL 16BIT DAC FOR MB86065
Manufacturer
Fujitsu Semiconductor America Inc
Specifications of DK86065-2
Number Of Dac's
1
Number Of Bits
14
Outputs And Type
1, Differential
Sampling Rate (per Second)
1G
Data Interface
Serial
Dac Type
Current
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
MB86065
For Use With
865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
865-1011
Contents
1
2
3
4
5
Page 2 of 56
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 DAC Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3 DAC Core Current Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5 Analog Output Reference Resistor . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.6 Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.7 Reset and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1 Programming a Read/Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Waveform Memory Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 Dual Port, Interleaved LVDS Data via the WMM . . . . . . . . . . . . . . . 22
3.2 Waveform Memory Module Operation. . . . . . . . . . . . . . . . . . . . . . . 23
3.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2 Digital Interface Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.4 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.5 Dynamic Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.6 Clock Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.7 Serial Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . 34
4.8 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2 Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3 Package Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.2.1
1.2.2
1.2.3
1.6.1
3.2.1
3.2.2
Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DAC Core Clocks Programmable Delays . . . . . . . . . . . . . . . 6
Waveform Memory Module Clock Programmable Delay . . . 7
Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Loop Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data from the LVDS Interface. . . . . . . . . . . . . . . . . . . . . . . 12
Adjusting the Input Data Timing . . . . . . . . . . . . . . . . . . . . . 13
Data from the Waveform Memory Module . . . . . . . . . . . . . 14
Frequency Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Waveform Memory Access via the Serial Interface . . . . . . 24
Writing Data into the Memories. . . . . . . . . . . . . . . . . . . . . . 26
Production
Copyright © 2004-2007 Fujitsu Microelectronics Europe GmbH
MB86065 14-bit 1+GSa/s DAC
September 2007 Version 1.01
FME/MS/DAC80S/DS/5344