DK86065-2 Fujitsu Semiconductor America Inc, DK86065-2 Datasheet - Page 6

• Manufacturer Part Number: DK86065-2
• Description: KIT EVAL 16BIT DAC FOR MB86065
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of DK86065-2

• Number Of Dac's: 1
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MB86065
• For Use With: 865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1011

1.1.2 DAC Core Clocks Programmable Delays
The DAC core clocks contain programmable delays. These allow adjustment to the point at which
data is clocked into the DAC core and when the analog portion of the DAC subsequently latches the
data. The delay settings are programmed through register DAC CORE CLOCK DELAYS, bits
dac_clk_dly and dac_latch_dly. Based on detailed evaluation by Fujitsu these registers should be
programmed in accordance with the recommendations given in Table 1.
Note: Bold type indicates default setting. See Appendix A.
Page 6 of 56
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
dac_latch_dly
inv_latch_clk
dac_clk_dly
inv_dac_clk
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
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Table 1: DAC Core Register: DAC CORE CLOCK DELAYS [0x1B2]
3
7
0
0
0
1
0
0
1
:
:
:
:
Production
Reg Bits
Reg Bits
Reg Bits
Reg Bits
2
6
0
1
1
1
0
1
1
:
:
:
:
8
9
0
1
0
1
5
0
0
0
1
0
0
1
:
:
:
:
0
4
0
0
1
1
0
0
1
:
:
:
:
Minimum (* Recommended for normal operation *)
Medium (default)
Required for 1+ GSa/s mode
Maximum
Minimum (* Recommended for normal & 1+GSa/s modes *)
Medium (default)
Maximum
Default (* Recommended for normal operation *)
Required for 1+ GSa/s mode
Default (* Recommended for normal & 1+GSa/s modes *)
DAC Core Analog Latch Clock Inversion
DAC Core Analog Latch Clock Delay
Copyright © 2004-2007 Fujitsu Microelectronics Europe GmbH
DAC Core Digital Clock Inversion
DAC Core Digital Clock Delay
MB86065 14-bit 1+GSa/s DAC
(0 - 1.5ns, 100ps steps)
(0 - 1.5ns, 100ps steps)
September 2007 Version 1.01
FME/MS/DAC80S/DS/5344