DK86065-2 Fujitsu Semiconductor America Inc, DK86065-2 Datasheet - Page 5

• Manufacturer Part Number: DK86065-2
• Description: KIT EVAL 16BIT DAC FOR MB86065
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of DK86065-2

• Number Of Dac's: 1
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MB86065
• For Use With: 865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1011

September 2007 Version 1.01
FME/MS/DAC80S/DS/5344
MB86065 14-bit 1+GSa/s DAC
1.1
The device requires an input clock at half the DAC conversion rate, with sufficient spectral purity to
not impact the target analog output performance. The DAC core is clocked on both rising and falling
edges of the input clock. This forms an effect of two interleaved converters in the DAC core. A
characteristic of this architecture is a suppressed image of the generated signal, appearing reflected
about Fs(dac)/4 = (Fclk-Fsig). Any duty cycle error in the input clock will exacerbate this image. This
can be minimised by trimming the differential DC offset at the clock input pins.
1.1.1 Input Clock
The input clock should be applied to the MB86065 through input pins CLKIN and CLKINB. The device
is designed to accept a differential sinusoidal clock. Once on chip and converted to CMOS the clock
is distributed to a number of blocks throughout the device. The DAC core is clocked directly from the
input clock buffer to ensure minimal degradation to the clock’s purity.
Copyright © 2004-2007 Fujitsu Microelectronics Europe GmbH
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
Loop clock output
Loop clock input
Clock
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
Clock input
X_RESET
Operation above 1GSa/s is supported by programming the appropriate register bit settings
documented in Section 1.1.2 (and Section 1.1.3 when using WMM data), subject to the
specified minimum & maximum clock frequency.
wmm_clk_dly
inv_wmm_clk
en_wmm_clk
LVDS
LVDS
0x1C4 – pg21
0x1C1 - pg6
0x1C1 – pg7
RF
loop_clk_dly
0x1C1 - pg9
Waveform Memory Module
en_ref_clk
0x1C4 - pg7
en_int_term
en_int_term
0x1C4 - pg11
0x1C4 - pg11
Clock to
Figure 2 Clock Distribution
dac_clk_dly
inv_dac_clk
0x1B2 – pg6
0x1B2 - pg6
(Located in WMM)
clkout1_cfg
clkout2_cfg
÷ 2
0x00 - pg7
0x00 - pg7
÷ 4
÷ N
÷ 8
Production
Clocks to
DAC core
dac_latch_dly
inv_latch_clk
0x1B2 – pg6
0x1B2 - pg6
clkout1_clk_dly
pdn_outcks
clkout2_clk_dly
0x1C3 - pg16
0x1C1 - pg7
0x1C1 - pg8
en_int_term
0x1C4 - pg11
Clock output 1
LVDS
Clock output 2
LVDS
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