DK86065-2 Fujitsu Semiconductor America Inc, DK86065-2 Datasheet - Page 25

• Manufacturer Part Number: DK86065-2
• Description: KIT EVAL 16BIT DAC FOR MB86065
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of DK86065-2

• Number Of Dac's: 1
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MB86065
• For Use With: 865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1011

September 2007 Version 1.01
FME/MS/DAC80S/DS/5344
MB86065 14-bit 1+GSa/s DAC
The WMM [EVEN/ODD] RAM CTRL registers prog_addr fields are used to define the start address
of the waveform. These fields should be set to 0 in order to store a full 16k point waveform. For the
multiple waveform mode, the number entered into these fields is the start location within the 2k x 64-
bit ODD/EVEN RAM element that the waveform is to be stored. One address location in this field
translates to eight waveform vector points because four points are stored at each address of the ODD
and EVEN RAM blocks.
The WMM [EVEN/ODD] RAM CTRL registers prog_burst fields sets the length of the stored
waveform, defined as the number of waveform points divided by eight, minus one. Every RAM
address in each of the ODD, EVEN, RAM A and RAM B memories corresponds to a 64-bit location.
Each location is divided into four 16-bit samples.
Figure 16 shows an example of how a 32 point vector is stored. In this example prog_addr is set to
0 and prog_burst = 3.
Copyright © 2004-2007 Fujitsu Microelectronics Europe GmbH
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
Table 17: Waveform Memory Module Registers: WMM [EVEN/ODD] RAM CTRL [0x12/0x22]
ODD] RAM CTRL
WMM [EVEN/
[21:11]
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
(bits)
[10:0]
When programming the WMM on-chip memories ensure that the Clock Input (f
greater than 16 times the serial interface clock frequency (f
22
23
24
25
prog_sel(1)
prog_sel(2)
prog_burst
prog_addr
prog_start
prog_rw
Label
RAM access start address
RAM access burst size
Access burst size should be programmed as ((No. of points/8) - 1)
A value of zero indicates a single word access
RAM serial interface access mode
0 = Read mode (default)
1 = Write mode
RAM write select (1). Dependent on prog_sel(2) setting
0 = Write data to RAM A (default)
1 = Write data to RAM B
RAM write select (2)
0 = prog_sel(1) operates as normal (default)
1 = Writes the same data to both RAM A and RAM B
RAM Access Controller control
0 = Cycle through vector address range (default)
1 = Program RAMs
This bit is self clearing
Function
Production
sclk
) for correct operation.
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Clk
) is