DK86065-2 Fujitsu Semiconductor America Inc, DK86065-2 Datasheet - Page 8

• Manufacturer Part Number: DK86065-2
• Description: KIT EVAL 16BIT DAC FOR MB86065
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of DK86065-2

• Number Of Dac's: 1
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MB86065
• For Use With: 865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1011

Also, programmable delay stages are provided in both CLK1_OUT and CLK2_OUT outputs. These
clock output delays are programmed through register SYSTEM CLOCK DELAYS clkout1_clk_dly
and clkout2_clk_dly. See Table 6 and Table 7.
Page 8 of 56
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
clkout1_clk_dly
clkout2_clk_dly
clkout1_cfg
clkout2_cfg
Table 5: Waveform Memory Module Register: WMM CONFIG [0x00] (Part 1 of 2)
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
Table 6: DAC Core Register: SYSTEM CLOCK DELAYS [0x1C1] (Part 2 of 4)
Table 7: DAC Core Register: SYSTEM CLOCK DELAYS [0x1C1] (Part 3 of 4)
Label
Label
Label
The clock outputs are designed to drive a doubly-terminated LVDS line (7mA drive into a
bridged 50 load) for the best possible signal integrity. 100 termination resistors should
be connected across the Q and Q signals at each end of the differential line. Enabling the
internal LVDS terminations provides the required source termination on-chip.
3
7
3
0
0
1
1
0
1
0
1
:
:
Production
Reg Bits
Reg Bits
Reg Bits
2
6
2
0
1
0
1
0
1
0
1
:
:
1
5
1
0
0
1
1
0
1
0
1
:
:
0
4
0
0
1
0
1
0
1
0
1
:
:
Clock output 1 = clock input (default)
Clock output 1 = clock input divided by 2
Clock output 1 = clock input divided by 4
Clock output 1 = clock input divided by 8
Clock output 2 = clock input (default)
Clock output 2 = clock input divided by 2
Clock output 2 = clock input divided by 4
Clock output 2 = clock input divided by 8
Minimum (default)
Maximum
Minimum (default)
Maximum
Divided Clock Output Configuration
Copyright © 2004-2007 Fujitsu Microelectronics Europe GmbH
MB86065 14-bit 1+GSa/s DAC
(0 - 1.5ns, 100ps steps)
(0 - 1.5ns, 100ps steps)
Clock Output Delay
Clock Output Delay
September 2007 Version 1.01
FME/MS/DAC80S/DS/5344