MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 112
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 112 of 117
- Download datasheet (2Mb)
System Design Information
Figure 69
112
2. Populate this with a 10-Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No Connect, some debug tools may use pin 12 as an additional GND pin for
5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL
6. Asserting SRESET causes a machine check interrupt to the e500 core.
1. The COP port and target board should be able to independently assert HRESET and TRST to the processor
Notes:
in order to fully control the processor as shown here.
improved signal integrity.
testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be
closed to position B.
COP Connector
Physical Pinout
11
13
15
shows the JTAG interface connection.
1
1
3
5
7
9
No pin
KEY
10
12
16
4
6
8
2
Board Sources
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
From Target
(if any)
14
13
11
15
10
12
16
SRESET
HRESET
4
6
5
8
9
1
3
7
2
3
COP_CHKSTP_IN
COP_CHKSTP_OUT
COP_VDD_SENSE
Figure 69. JTAG Interface Connection
COP_TMS
COP_TDO
COP_TDI
COP_TCK
COP_SRESET
COP_TRST
COP_HRESET
NC
NC
NC
4
B
2
5
A
10 kΩ
10 Ω
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
OV
DD
SRESET
HRESET
TRST
CKSTP_OUT
CKSTP_IN
TMS
TDO
TDI
TCK
Freescale Semiconductor
1
1
6
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