MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 67

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
•
SDn_REF_CLK
SDn_REF_CLK
SDn_REF_CLK
SDn_REF_CLK
— For external DC-coupled connection, as described in
— For external AC-coupled connection, there is no common mode voltage requirement for the
Single-ended Mode
— The reference clock can also be single-ended. The SDn_REF_CLK input amplitude
— The SDn_REF_CLK input average voltage must be between 200 and 400 mV.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or
Figure 46. Differential Reference Clock Input DC Requirements (External DC-Coupled)
Figure 47. Differential Reference Clock Input DC Requirements (External AC-Coupled)
Clock Receiver
requirement for average voltage (common mode voltage) to be between 100 and 400 mV.
Figure 46
scheme.
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above
the command mode voltage (SGND_SRDSn).
input requirement for AC-coupled connection scheme.
(single-ended swing) must be between 400 and 800 mV peak-peak (from Vmin to Vmax) with
SDn_REF_CLK either left unconnected or tied to ground.
the SerDes reference clock input requirement for single-ended signaling mode.
AC-coupled externally. For the best noise performance, the reference of the clock could be DC
or AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as
the clock input (SDn_REF_CLK) in use.
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
shows the SerDes reference clock input requirement for DC-coupled connection
200 mV < Input Amplitude or Differential Peak < 800 mV
200 mV < Input Amplitude or Differential Peak < 800 mV
Characteristics,” the maximum average current requirements sets the
Figure 47
Section 16.2.1, “SerDes Reference
shows the SerDes reference clock
High-Speed Serial Interfaces (HSSI)
100 mV < Vcm < 400 mV
Vmin > Vcm - 400 mV
Vmax < Vcm + 400 mV
Vmax < 800 mV
Figure 48
Vmin > 0 V
Vcm
shows
67