MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 77
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 77 of 117
- Download datasheet (2Mb)
17.4.3
Table 60
at the component pins.
Freescale Semiconductor
UI
V
T
RX-EYE
RX-DIFFp-p
Symbol
defines the specifications for the differential input at all receivers. The parameters are specified
Figure 56. Minimum Transmitter Timing and Voltage Output Compliance Specifications
Differential Receiver (RX) Input Specifications
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
(D+ D– Crossing Point)
Unit interval
Differential peak-to-
peak input voltage
Minimum receiver
eye width
V
RX-DIFF
Parameter
Table 60. Differential Receiver (RX) Input Specifications
= 0 mV
566 mV (3 dB) >= V
0.07 UI = UI – 0.3 UI (J
399.88
0.175
Min
0.4
V
V
TX-DIFFp-p-MIN
TX-DIFFp-p-MIN
[De-Emphasized Bit]
Nom
[Transition Bit]
[Transition Bit]
400
—
—
TX-DIFFp-p-MIN
400.12
1.200
Max
= 800 mV
= 800 mV
—
TX-TOTAL-MAX
>= 505 mV (4 dB)
Units
ps
UI
V
(D+ D– Crossing Point)
)
Each UI is 400 ps ± 300 ppm. UI does not
account for spread spectrum clock dictated
variations. See Note 1.
V
See Note 2.
The maximum interconnect media and
transmitter jitter that can be tolerated by the
receiver can be derived as T
= 1 – T
See Notes 2 and 3.
V
RX-DIFFp-p
TX-DIFF
RX-EYE
= 0 mV
= 2 × |V
= 0.6 UI.
Comments
RX-D+
– V
RX-MAX-JITTER
RX-D–
PCI Express
|
77
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