MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 33
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MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
8.5.2.2
Table 31
Figure 14
Figure 15
8.6
This section describes the MII transmit and receive AC timing specifications.
Freescale Semiconductor
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
RX_CLK clock period
RX_CLK duty cycle
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RX_CLK to RXD[7:0], RX_DV, RX_ER hold time
RX_CLK clock rise (20%–80%)
RX_CLK clock fall time (80%–20%)
Note:
1. The symbols used for timing specifications follow the pattern of t
inputs and t
timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
going to the high state (H) or setup time. Also, t
input signals (D) went invalid (X) relative to the t
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of t
is used with the appropriate letter: R (rise) or F (fall).
provides the GMII receive AC timing specifications.
MII AC Timing Specifications
provides the AC test load for eTSEC.
shows the GMII receive AC timing diagram.
(first two letters of functional block)(reference)(state)(signal)(state)
GMII Receive AC Timing Specifications
Parameter/Condition
RXD[7:0]
RX_CLK
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
RX_DV
RX_ER
Output
GRX
Table 31. GMII Receive AC Timing Specifications
Figure 15. GMII Receive AC Timing Diagram
represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention
t
t
GRXH
GRDVKH
Figure 14. eTSEC AC Test Load
t
GRX
Z
GRDXKL
GRX
0
= 50 Ω
clock reference (K) going to the low (L) state or hold time. Note that, in
symbolizes GMII receive timing (GR) with respect to the time data
t
GRXH
Symbol
t
t
GRDXKH
GRDVKH
t
t
t
GRXR
GRXF
GRX
t
/t
GRXF
GRX
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
1
t
GRDXKH
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Min
R
2.0
0.5
—
—
—
35
L
t
GRXR
= 50 Ω
Typ
8.0
—
—
—
—
—
LV
GRDVKH
DD
/2
Max
1.0
1.0
65
—
—
—
symbolizes GMII receive
RX
clock reference (K)
Unit
ns
ns
ns
ns
ns
%
Notes
—
—
—
—
—
—
for
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