MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 14

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Input Clocks
4.1
Table 5
At recommended operating conditions (see
4.1.1
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference
emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise
magnitude in order to meet industry and government requirements. These clock sources intentionally add
long-term jitter in order to diffuse the EMI spectral content. The jitter specification given in
considers short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle output jitter
should meet the MPC8544E input cycle-to-cycle jitter requirement. Frequency modulation and spread are
separate concerns, and the MPC8544E is compatible with spread spectrum sources if the recommendations
listed in
It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies
must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is
operated at its maximum rated e500 core frequency should avoid violating the stated limits by using
down-spreading only.
14
At recommended operating conditions. See
SYSCLK frequency
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle
SYSCLK jitter
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
2. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.
3. This represents the total input jitter—short- and long-term.
4. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow
Frequency modulation
Frequency spread
Note:
1. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies, must meet the
cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.
minimum and maximum specifications given in
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to
settings.
provides the system clock (SYSCLK) AC timing specifications for the MPC8544E.
Table 6
System Clock Timing
Parameter/Condition
SYSCLK and Spread Spectrum Sources
are observed.
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Table 6. Spread Spectrum Clock Source Recommendations
Parameter
Section 19.2, “CCB/SYSCLK PLL Ratio,”
Table 5. SYSCLK AC Timing Specifications
Table
Table
2) with OV
2.
Table
t
KHK
DD
Symbol
f
t
t
SYSCLK
SYSCLK
KH
/t
= 3.3 V ± 165 mV.
5.
—
SYSCLK
, t
KL
Min
7.5
0.6
33
40
—
and
Min
20
0
Section 19.3, “e500 Core PLL Ratio,”
Typical
1.0
—
—
—
—
Max
±150
Max
30.3
1.0
133
60
2.1
60
Freescale Semiconductor
Unit
MHz
ns
ns
ps
Unit
%
kHz
%
Table 5
Notes
for ratio
Notes
3, 4
—
—
—
1
2
1