MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 113
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 113 of 117
- Download datasheet (2Mb)
21.10 Guidelines for High-Speed Interface Termination
This section provides guidelines for when the SerDes interface is either not used at all or only partly used.
21.10.1 SerDes Interface Entirely Unused
If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in
this section. However, the SerDes must always have power applied to its supply pins.
The following pins must be left unconnected (float):
The following pins must be connected to GND:
21.10.2 SerDes Interface Partly Unused
If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins
should be terminated as described in this section.
The following pins must be left unconnected (float) if not used:
The following pins must be connected to GND if not used:
21.11 Guideline for PCI Interface Termination
PCI termination, if not used at all, is done as follows.
Option 1
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
SD_TX[0:7]
SD_TX[0:7]
SD_RX[0:7]
SD_RX[0:7]
SD_REF_CLK
SD_REF_CLK
SD_TX[0:7]
SD_TX[0:7]
SD_RX[0:7]
SD_RX[0:7]
SD_REF_CLK
SD_REF_CLK
If PCI arbiter is enabled during POR,
All AD pins will be driven to the stable states after POR. Therefore, all ADs pins can be floating.
All PCI control pins can be grouped together and tied to OV
It is optional to disable PCI block through DEVDISR register after POR reset.
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
DD
through a single 10-kΩ resistor.
System Design Information
113
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