EVAL-ADUC7032QSPZ Analog Devices Inc, EVAL-ADUC7032QSPZ Datasheet - Page 60

• Manufacturer Part Number: EVAL-ADUC7032QSPZ
• Description: EVAL DEV QUICK START ADUC7032
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCUr

Specifications of EVAL-ADUC7032QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• For Use With/related Products: ADuC7032
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7032-8L
ADuC7032-8L SYSTEM CLOCKS
The ADuC7032-8L integrates a highly flexible clocking system
that can be clocked from one of three sources: an integrated on-
chip precision oscillator, an integrated on-chip low power oscil-
lator, or an external watch crystal. These three options are shown
in Figure 27.
Each of the internal oscillators is divided by four to generate a
clock frequency of 32.768 kHz. The PLL locks onto a multiple
(625) of 32.768 kHz, supplied by either of the internal oscillators
or the external crystal, providing a stable 20.48 MHz clock for
the system. The core can operate at this frequency or at binary
submultiples of it, allowing power saving if peak performance is
not required.
By default, the PLL is driven by the low power oscillator, which
generates a 20.48 MHz clock source. The ARM7TDMI core is
OSCILLATOR
PRECISION
CLOCK
CORE
CORE CLOCK
PLL OUTPUT
(20.48MHz)
1
8
PLL LOCK
PRECISION
MCU
131kHz
CLOCK
2
DIV 4
CD
1
EXTERNAL
32.768kHz
SPI
PRECISION
32.768kHz
EXTERNAL CRYSTAL
CONTROLLER
Figure 27. ADuC7032-8L System Clock Generation
PLL OUTPUT
(OPTIONAL)
CIRCUITRY
CRYSTAL
20.48MHz
PLLCON
FLASH
CORE CLOCK
PLL
LOW POWER
32.768kHz
LOW POWER
OSCILLATOR
Rev.0 | Page 60 of 116
ECLK 2.5MHz
CLOCK
ADC
DIVIDER
CLOCK
LOW POWER
UART
131kHz
ADCMDE
DIV 4
ADC
driven by a CD divided clock derived from the output of the
PLL. By default, the CD divider is configured to divide the PLL
output by two, which generates a core clock of 10.24 MHz.
The divide factor can be modified to generate a binary weighted
divider factor from 1 to 128, which can be altered dynamically
by user code.
The ADC is driven by the output of the PLL, divided to give an
ADC clock source of 512 kHz. In low-power mode, the ADC
clock source is switched from the standard 512 kHz to the low
power 131 kHz oscillator.
It should also be noted that the low power oscillator drives both
the watchdog and core wake-up timers through a divide-by-4
circuit. A detailed block diagram of the ADuC7032-8L clocking
system is shown in Figure 27.
CORE CLOCK
CORE CLOCK
CORE CLOCK
CORE CLOCK
OSCILLATOR
LOW POWER
LOW POWER
LOW POWER
LOW POWER
LOW POWER
LOW POWER
LOW POWER
PLL OUTPUT
PRECISION
EXTERNAL
EXTERNAL
PRECISION
EXTERNAL
PRECISION
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
GPIO_5
GPIO_8
131kHz
(5MHz)
SYNCHRONIZATION
HIGH ACCURACY
CALIBRATION
CALIBRATION
LOW POWER
WATCHDOG
COUNTER
COUNTER
LIFE TIME
WAKE-UP
LIN H/W
TIMER0
TIMER1
TIMER2
TIMER3
TIMER4
STI